High Level Programming of Reconfigurable Hardware 5 (U04213)

? Credit Points : 20 ? SCQF Level : 11 ? Acronym : EEL-5-ELPRH

The aim of this course is to produce students who are capable of designing reconfigurable hardware (FPGAs) from a high level language.

? Keywords : FPGAs, High Level Programming, Handel-C, Electronic System Level design

Entry Requirements

? Pre-requisites : 00441 Digital Electronics or U01900 Computer Design or equivalent AND U00481 Electrical Engineering Methods or CS0004 Computer Programming Skills and Concepts 1 or equivalent

? Co-requisites : NA

Subject Areas

Home subject area

Electronics, (School of Engineering and Electronics, Schedule M)

Delivery Information

? Normal year taken : 5th year

? Delivery Period : Semester 2 (Blocks 3-4)

? Contact Teaching Time : 2 hour(s) per week for 10 weeks

? Other Required Attendance : 3 hour(s) per week for 4 weeks

All of the following classes

Type	Day	Start	End	Area
Lecture	Wednesday	10:00	10:50	KB
Lecture	Thursday	10:00	10:50	KB

Summary of Intended Learning Outcomes

1. Knowledge and understanding of:
I. The role of Field Programmable Gate Arrays (FPGAs) as modern computing platforms;
II. A range of FPGA design flows including High Level Language (HLL) design flows
2. Intellectual
I. Ability to choose between different FPGA design techniques, use them to develop FPGA-based applications and evaluate the resulting implementations
3. Practical
I. Ability to use an HLL-based FPGA design suite to develop applications on FPGAs

Assessment Information

Written Examination: 50%
Practicals: 50%

Four 3-hour lab sessions would be run in this course. Students will submit the work produced at the end of each session, which will be assessed.