Undergraduate Course: Digital System Design 4 (ELEE10007)
Course Outline
| School |
School of Engineering |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 10 (Year 4 Undergraduate) |
Credits |
10 |
| Home subject area |
Electronics |
Other subject area |
None |
| Course website |
None |
|
|
| Course description |
This course is lecture based and is taken by all students taking the forth year of electronics and/or electrical engineering degree in Semester 2. It comprises one 20 lecture module. The course aims to present the principles of design re-use in the context of System-on-Chip (SoC) technology. The design and selection of soft, firm, and hard IP blocks are considered. Emerging design practices and standards are reviewed. Two target technologies are addressed: deep-submicron ASICs and field programmable gate arrays (FPGAs). |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 2, Available to all students (SV1)
|
WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | | 1-11 | 09:00 - 09:50 | | | | | | King's Buildings | Lecture | | 1-11 | | | 10:00 - 10:50 | | | | King's Buildings | Lecture | | 1-11 | | | | 10:00 - 10:50 | |
| First Class |
Week 1, Monday, 09:00 - 09:50, Zone: King's Buildings. Room 5327, James Clerk Maxwell Building |
Summary of Intended Learning Outcomes
At the conclusion of the exercise the students should be able to
1. Understand architectural design and synthesis principles;
2. Understand the concept of Hardware Description Languages (HDLs);
3. Understand the transformation of an algorithm from specification to an RTL (described with a Hardware Description Language such as Verilog-HDL);
4. Understand the technological conditions behind the need for greater design re-use for IC systems;
5. Differentiate between the different types of intellectual property (IP) blocks, their advantages and disadvantages;
6. Evaluate the appropriateness of a particular IP block for a given application;
7. Assess a piece of soft IP using the QIP metric;
8. Assess a piece of soft IP using industrial tools such as DesignChecker;
9. Understand the generation of a Hard IP;
10. Apply the design guidelines for IP block authoring;
11. Understand the effects of DSM technology on the CAD flow for ASIC design;
12. Be familiar with the DSM ASIC design methodology;
13. Be familiar with general HDL coding guidelines for reuse;
14. Be familiar with low power design techniques;
15. Understand high level synthesis techniques for high performance implementations;
16. Understand advanced computer architectures;
17. Understand datapath architectures used for high performance implementations. |
Assessment Information
| Assessment will be based on a single written paper of 90 minutes duration. |
| Please see Visiting Student Prospectus website for Visiting Student Assessment information |
Special Arrangements
| Not entered |
Contacts
| Course organiser |
Dr Tughrul Arslan
Tel: (0131 6)50 5592
Email: T.Arslan@ed.ac.uk |
Course secretary |
Mrs Laura Smith
Tel: (0131 6)50 5690
Email: laura.smith@ed.ac.uk |
|
copyright 2010 The University of Edinburgh -
1 September 2010 5:58 am
|
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