Postgraduate Course: CMOS IC testing (ELEE11046)
Course Outline
| School |
School of Engineering |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 11 (Postgraduate) |
Credits |
10 |
| Home subject area |
Electronics |
Other subject area |
None |
| Course website |
None |
|
|
| Course description |
Today?s integrated circuits, whether digital or analogue, are enormously complex, and if adequate thought is not given to their testing during the design process it will not be possible to test them when they return from fabrication.
A prototype chip will often exhibit faults, or non-idealities, and if consideration has not been given as to how to detect these the chip will be a failure, because it will not be possible to find the reason for the problems encountered, and hence how to fix them.
A production chip will be made in large volumes and cost is critical. Today the cost of the fabrication of the chip can be less than the cost of testing the chip, so it is vital that the cost of testing, and hence the time taken to test the chip, is minimised.
There exist techniques that ease the testing process, or even make chips test themselves. It is also possible to design chips that can reconfigure themselves to work around a fault. All these techniques result in the chip being larger, so the cost of the silicon increases, but the cost of testing falls dramatically. This module will examine these techniques and concepts, and will investigate the tradeoffs to be made. |
Entry Requirements
| Pre-requisites |
|
Co-requisites |
|
| Prohibited Combinations |
|
Other requirements |
None
|
| Additional Costs |
None |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 2, Available to all students (SV1)
|
WebCT enabled: No |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | | 1-11 | 09:00 - 09:50 | | | | |
| First Class |
First class information not currently available |
Summary of Intended Learning Outcomes
| Students will understand how to best design integrated circuits so that they can be efficiently, quickly and cheaply tested. |
Assessment Information
| 100% exam |
| Please see Visiting Student Prospectus website for Visiting Student Assessment information |
Special Arrangements
| Not entered |
Contacts
| Course organiser |
Dr Alister Hamilton
Tel: (0131 6)50 5597
Email: Alister.Hamilton@ed.ac.uk |
Course secretary |
Mrs Kim Orsi
Tel: (0131 6)50 5687
Email: Kim.Orsi@ed.ac.uk |
|
copyright 2010 The University of Edinburgh -
1 September 2010 5:58 am
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