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Degree Regulations & Programmes of Study 2010/2011
- ARCHIVE as at 1 September 2010 for reference only
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DRPS : Course Catalogue : School of Informatics : Informatics

Undergraduate Course: Informatics 2C - Introduction to Computer Systems (INFR08018)

Course Outline
School School of Informatics College College of Science and Engineering
Course type Standard Availability Available to all students
Credit level (Normal year taken) SCQF Level 08 (Year 2 Undergraduate) Credits 10
Home subject area Informatics Other subject area None
Course website None
Course description This course is concerned with the design, implementation and engineering of digital computer systems. It offers an introduction to the internal structure of digital computers.
Entry Requirements
Pre-requisites Students MUST have passed: Informatics 1 - Computation and Logic (INFR08012) AND Informatics 1 - Data and Analysis (INFR08015) AND Informatics 1 - Functional Programming (INFR08013) AND Informatics 1 - Object-Oriented Programming (INFR08014)
Co-requisites
Prohibited Combinations Other requirements None
Additional Costs none
Information for Visiting Students
Pre-requisites none
Prospectus website http://www.ed.ac.uk/studying/visiting-exchange/courses
Course Delivery Information
Delivery period: 2010/11 Semester 1, Available to all students (SV1) WebCT enabled:  No Quota:  None
Location Activity Description Weeks Monday Tuesday Wednesday Thursday Friday
CentralLecture1-11 15:00 - 15:50
CentralLecture1-11 15:00 - 15:50
First Class Week 1, Tuesday, 15:00 - 15:50, Zone: Central. Lecture Theatre B, David Hume Tower
Summary of Intended Learning Outcomes
- Demonstrate an understanding of binary representation and basic operations on binary data.
- Demonstrate an understanding of key concepts in computer architecture, including: exceptions, interrupts, virtual memory, processes and pipelined execution.
- Sketch the design of a simple processor and explain how it operates.
- Demonstrate knowledge of I/O devices and the means by which they interface to a processor and its memory system.
- Demonstrate an understanding of the design and operation of important combinational and sequential components within a processor, such as adders, registers, and state machines.
- Demonstrate understanding of an execution pipeline, based on the MIPS architecture.
Assessment Information
Written Examination - 75%
Assessed Assignments - 25%
Oral Presentations - 0%

There will be at least one assessed exercise.
Please see Visiting Student Prospectus website for Visiting Student Assessment information
Special Arrangements
Not entered
Contacts
Course organiser Dr Jacques Fleuriot
Tel: (0131 6)50 9342
Email: Jacques.Fleuriot@ed.ac.uk		 Course secretary Ms Kendal Reid
Tel: (0131 6)50 5194
Email: kr@inf.ed.ac.uk
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copyright 2010 The University of Edinburgh - 1 September 2010 6:09 am