Undergraduate Course: Computer Architecture (INFR09009)
Course Outline
School |
School of Informatics |
College |
College of Science and Engineering |
Course type |
Standard |
Availability |
Available to all students |
Credit level (Normal year taken) |
SCQF Level 09 (Year 3 Undergraduate) |
Credits |
10 |
Home subject area |
Informatics |
Other subject area |
None |
Course website |
http://www.inf.ed.ac.uk/teaching/courses/car |
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Course description |
Computer architecture is about optimising the design of computer hardware and software under constraints of time, cost and power consumption. Over the years, improvements intechnology and advances in computer architecture have resulted in huge increases in computer performance. This course examines the fundamentals of high-performance computer architecture and looks at how the interface between hardware and software (architecture and compiler) influences performance. |
Entry Requirements
Pre-requisites |
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Co-requisites |
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Prohibited Combinations |
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Other requirements |
Successful completion of Year 2 of an Informatics Single or Combined Degree, or equivalent by permission of the School.
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Additional Costs |
None |
Course Delivery Information
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Delivery period: 2010/11 Semester 2, Available to all students (SV1)
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WebCT enabled: No |
Quota: None |
Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
Central | Lecture | | 1-11 | | | | 10:00 - 10:50 | | Central | Lecture | | 1-11 | 10:00 - 10:50 | | | | |
First Class |
Week 1, Monday, 10:00 - 10:50, Zone: Central. Seminar Room 2, Chrystal Macmillan Building |
Summary of Intended Learning Outcomes
1 - Describe the structure and operational characteristics of a pipelined microprocessor.
2 - Explain principles of: orthogonal instruction set design; pipeline hazards and interlocks; out of order execution; scoreboards and reservation stations and their use; branch prediction (both static and dynamic); and techniques (both software and hardware) for exploiting loop-level parallelism.
3 - Evaluate the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements.
4 - Explain the principle of memory locality and show how a memory hierarchy exploits the various forms of locality.
5 - Give an outline design of a memory hierarchy and specify reasonable parameters for each configuration point (capacity, associativity, block size, and write policies) at each level in the hierarchy.
6 - Describe the memory coherency issues involved when designing a multiprocessor system, and explain the behaviour of a typical cache coherency protocol. |
Assessment Information
Written Examination 75
Assessed Assignments 25
Oral Presentations 0
Assessment
Two practical exercises.
If delivered in semester 1, this course will have an option for semester 1 only visiting undergraduate students, providing assessment prior to the end of the calendar year. |
Please see Visiting Student Prospectus website for Visiting Student Assessment information |
Special Arrangements
Not entered |
Contacts
Course organiser |
Dr Marcelo Cintra
Tel: (0131 6)50 5118
Email: mc@inf.ed.ac.uk |
Course secretary |
Miss Tamise Totterdell
Tel: 0131 650 9970
Email: t.totterdell@ed.ac.uk |
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copyright 2010 The University of Edinburgh -
1 September 2010 6:09 am
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