Undergraduate Course: Computer Design (INFR09010)
Course Outline
| School |
School of Informatics |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 09 (Year 3 Undergraduate) |
Credits |
10 |
| Home subject area |
Informatics |
Other subject area |
None |
| Course website |
http://www.inf.ed.ac.uk/teaching/courses/cd |
|
|
| Course description |
This course provides an introduction to the fundamental concepts of the different ways computers can be analysed and designed. The course does not look at the differences between machines with different types of instruction set, nor does it cover design techniques for extracting maximum performance from computers - these aspects of computer hardware are covered in the Computer Architecture course. The issues and techniques covered in the Computer Design course are relevant to the design of all computers, regardless of their particular architecture.
The course is partitioned into three sections. The short first section revises the design of combinational and sequential logic. The second section demonstrates how to analyse and design systems of the complexity of a simple CPU or I/O controller. The third section of the course covers the design of a complete computer capable of executing assembly code programs and different control strategies for performing I/O. |
Entry Requirements
| Pre-requisites |
|
Co-requisites |
|
| Prohibited Combinations |
|
Other requirements |
Successful completion of Year 2 of an Informatics Single or Combined Degree, or equivalent by permission of the School.
|
| Additional Costs |
None |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 1, Available to all students (SV1)
|
WebCT enabled: No |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| Central | Lecture | | 1-11 | | | | 12:10 - 13:00 | | | Central | Lecture | | 1-11 | 12:10 - 13:00 | | | | |
| First Class |
Week 1, Monday, 12:10 - 13:00, Zone: Central. Room G.11, William Robertson Building |
|
| Delivery period: 2010/11 Semester 1, Part-year visiting students only (VV1)
|
WebCT enabled: No |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| Central | Lecture | | 1-11 | 12:10 - 13:00 | | | | | | Central | Lecture | | 1-11 | | | | 12:10 - 13:00 | |
| First Class |
Week 1, Monday, 12:10 - 13:00, Zone: Central. Room G.11, William Robertson Building |
Summary of Intended Learning Outcomes
1 - Build state machines to implement a circuit or system to a specification.
2 - Interconnect circuits for systems of higher complexity, specifically up to the complexity of the components required in a simple computer processor datapath.
3 - Analyse and synthesise circuits to control and sequence the flow of data within a simple cpu or microcontroller.
4 - Analyse and synthesise circuits to control and sequence the flow of data between a simple cpu, memory systems and input/output device controllers.
5 - Design and implement a microprogrammed controller for a given simple cpu architecture.
6 - Gain familiarity with: design and simulation software; designing systems with Verilog HDL; programming designs into a large field-programmable gate array device (FPGA); using an assembly language to implement a design in a programmable microcontroller. |
Assessment Information
Written Examination 75
Assessed Assignments 25
Oral Presentations 0
Assessment
There are four practical exercises for the course. All take place in the hardware lab. The first exercise introduces students to the software and hardware to be used by following a design tutorial all the way through to implementation on a FPGA. The second exercise gives students familiarity with a sequential logic design implemented in a programmable microcontroller. The third exercise requires the design and implementation of the microcode for a specified cpu data path to build a real computer on the FPGA board and a final exercise to program the processor to drive some I/O devices.
If delivered in semester 1, this course will have an option for semester 1 only visiting undergraduate students, providing assessment prior to the end of the calendar year. |
| Please see Visiting Student Prospectus website for Visiting Student Assessment information |
Special Arrangements
| Not entered |
Contacts
| Course organiser |
Dr Marcelo Cintra
Tel: (0131 6)50 5118
Email: mc@inf.ed.ac.uk |
Course secretary |
Miss Tamise Totterdell
Tel: 0131 650 9970
Email: t.totterdell@ed.ac.uk |
|
copyright 2010 The University of Edinburgh -
1 September 2010 6:09 am
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