Undergraduate Course: Electronics 3 (ELEE09015)
Course Outline
| School |
School of Engineering |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 9 (Year 3 Undergraduate) |
Credits |
20 |
| Home subject area |
Electronics |
Other subject area |
None |
| Course website |
http://www.see.ed.ac.uk/teaching/electronics/year3/elme3.html
|
Taught in Gaelic? |
No |
| Course description |
This course is lecture and laboratory based and is taken by all students taking the third year of an electrical and mechanical engineering degree and electronics and electrical engineering with management degree, in Semesters 1 and 2. It comprises one 20 lecture module, Digital Circuits and the Satway laboratory module.
Digital Circuits: Digital Circuits aims to build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for datapath and FSM design.
Satway: Satway is an exercise in analogue circuit design undertaken by all students in the third year of our BEng and MEng degree courses. The exercise is to design and realise the circuitry to display a television signal as a picture on a standard oscilloscope. The exercise is designed to use knowledge gained by students in the earlier years of their course and aims to act a "structured project" to act as an introduction to the more open ended type of final year project work carried out in the fourth and fifth years. Until this point in the course the students experience is largely of analysis of circuits supplied to them. In this exercise they are expected to synthesise their own designs and realise their own circuitry. |
Information for Visiting Students
| Pre-requisites |
None |
| Displayed in Visiting Students Prospectus? |
Yes |
Course Delivery Information
|
| Delivery period: 2010/11 Full Year, Available to all students (SV1)
|
WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | Digital Circuits | 1-11 | | 12:10 - 13:00 | | | | | King's Buildings | Lecture | Digital Circuits | 1-11 | | | | | 12:10 - 13:00 | | King's Buildings | Tutorial | Digital Circuits | 3-11 | 16:10 - 17:00 | | | | | | King's Buildings | Tutorial | Digital Circuits | 3-11 | | | | 16:10 - 17:00 | |
| First Class |
Week 1, Tuesday, 12:10 - 13:00, Zone: King's Buildings. Lecture Theatre 6301, JCMB |
| Exam Information |
| Exam Diet |
Paper Name |
Hours:Minutes |
Stationery Requirements |
Comments |
| Main Exam Diet S1 (December) | Electronics 3 | 1:30 | 12 sides | |
Summary of Intended Learning Outcomes
Digital Circuits:
1.Understand the concept of synthesis and modern digital circuit design;
2.Understand the need for optimisation;
3.Understand the steps involved in synthesis and identify different types of circuits;
4.Understand design methodologies using current computer aided design tools;
5.Understand digital circuit representation formats including high level hardware description languages such as Verilog-HDL;
6.Understand the general digital circuit structure;
7.Understand the concept of static timing analysis with use of cell delay and wireload models;
8.Understand binary arithmetic, number representation and coding, including 2?s complement and floating-point representations;
9.Understand the basic datapath structures, including adders and multipliers;
10.Design and analyse small synchronous digital circuits which incorporate D, T or JK Flip Flops;
11.Implement small synchronous circuit designs using discrete gates and flip-flops and programmable logic devices;
12.Understand synchronous flip-flops, setup and hold timing constraints;
13.Understand synchronous counters, non-binary synchronous counters, generalised small synchronous design methods;
14.Understand Moore and Mealy machines, sate diagrams, ASM charts;
15.Design synchronous sequence detectors;
16.Understand Programmable Logic Devices (PLDs).
Satway : At the conclusion of the exercise students should:
- be able to design voltage amplifier, ramp generator and sync. pulse separator circuits.
- be able to implement a multistage amplifier design which withstands the effects of inter-stage loading between successive stages.
- be able to implement effective decoupling in a design.
- be able to integrate a number of separate stages to implement a complete working system to a written specification.
- be able to document a design that they have carried out.
- be able to layout and implement a printed circuit board design. |
Assessment Information
| 1.5 Hours Examination in semester 1 (50%) + Laboratory Work in semester 2 (50%) |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Not entered |
| Transferable skills |
Not entered |
| Reading list |
Fundamentals of Logic Design: fourth edition, C. H. Roth, (West Publishing Company) 1992
Application-Specific Integrated Circuits, M.J.S. Smith, (Addison Wesley) 1997, ISBN 0 201 50022 1
Digital Integrated Circuits: A Design Perspective, J.M. Rabaey, Prentice Hall (1996), ISBN 0 13 1786091
HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL and Verilog, D.J. Smith, (Doone Publications) 1999, ISBN 0 9651934 3 8
The art of digital design, D. Winkel and F. Prosser, (Prentice hall) 1980
Electronic Logic Circuits, J.R. Gibson, (Edward Arnold) 1992 |
| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords |
Not entered |
Contacts
| Course organiser |
Dr Tughrul Arslan
Tel: (0131 6)50 5592
Email: T.Arslan@ed.ac.uk |
Course secretary |
Miss Nicola Marshall
Tel: (0131 6)50 5687
Email: Nicola.Marshall@ed.ac.uk |
|
copyright 2011 The University of Edinburgh -
13 January 2011 6:00 am
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