Undergraduate Course: Microelectronics 3 (ELEE09011)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Course type | Standard |
Availability | Available to all students |
| Credit level (Normal year taken) | SCQF Level 9 (Year 3 Undergraduate) |
Credits | 20 |
| Home subject area | Electronics |
Other subject area | None |
| Course website |
None |
Taught in Gaelic? | No |
| Course description | Microelectronic Devices: The objective of this module is to give students a comprehensive introduction to planar MOS devices, manufacturing technology and simple MOS circuits. The practical exercise that backs up this course is NICEWAY. The NICEWAY computer simulation laboratory is a technology design exercise where a MOS process is designed, using SUPREM, to meet a given specification.
Gateway: The Gateway laboratory covers the design, simulation and synthesis of synchronous systems using the verilog hardware description language. It is aims to giving the student an overview of the design cycle developing; the ability to design and test digital circuits in the verilog language, an understanding and use of the synthesis process to perform simple synthesis of behavioral verilog.
Niceway: The Niceway Exercise introduces students to the design of fabrication processes for integrated circuit manufacture. It supports the Microelectronic Devices module and gives students an awareness of process and device simulation, which is an important area of semiconductor technology. Students are set specifications for device properties such as junction depths, threshold voltages, sheet resistivities and oxide thicknesses and then use the commercial 2D process and device simulators TSUPREM4 and MEDICI to determine values for NMOS process variables which will yield these specifications. These include factors such as oxidation times and implant doses and energies. |
Information for Visiting Students
| Pre-requisites | None |
| Displayed in Visiting Students Prospectus? | Yes |
Course Delivery Information
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| Delivery period: 2011/12 Semester 1, Available to all students (SV1)
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WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | | 1-11 | | 10:00 - 10:50 | | | | | King's Buildings | Lecture | | 1-11 | | | | | 09:00 - 09:50 | | King's Buildings | Tutorial | | 1-11 | 14:00 - 14:50 | | | | | | King's Buildings | Tutorial | | 2-11 | | | | 14:00 - 14:50 | |
| First Class |
First class information not currently available |
| Exam Information |
| Exam Diet |
Paper Name |
Hours:Minutes |
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| Main Exam Diet S1 (December) | Microelectronics 3 | 1:30 | | | | Resit Exam Diet (August) | | 1:30 | | |
Summary of Intended Learning Outcomes
Microelectronic Devices: Understand the theory of MOSFET operation. Reproduce the I-V characteristics of contemporary devices. Follow the manufacturing process sequence for MOS wafers. Know which steps of the manufacturing process affect which characteristics or properties of the finished device, and in what way. Design and optimise simple MOS circuits. Understand the link among device physics, manufacturing process and circuit design; appreciate how, and to what extent, all three contribute to circuit performance.
Gateway: be able to design a shift/add multiplier in verilog; be able to code synchronous state machines in verilog; be able to synthesise digital circuits using verilog; be able to design test code to verify the functionality of a digital circuit; be able to document a design component in a brief form that communicates the important information required to understand and use the design.
Niceway: Design a basic fabrication process using the commercial software tools provided. Interpret doping profiles and device cross-sections for an MOS transistor at a point in its fabrication process. Explain qualitatively how and why device properties such as junction depth and sheet resistance will vary with changes in key process variables, and quote typical values for these. Explain the main features of the oxidation and implantation process. Explain why process and device simulation is important in the manufacture of IC's and the limitations and advantages of 1-D, 2-D and 3-D simulators. State the meaning of standard processing terms such as "field oxide", "implant dose", "bird's beak" and "sheet resistance". |
Assessment Information
Microelectronic Devices - 1.5 hour examination (50%)
Gateway and Niceway - Laboratory based (50%) |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Not entered |
| Transferable skills |
Not entered |
| Reading list |
Not entered |
| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords | Not entered |
Contacts
| Course organiser | Dr Rebecca Cheung
Tel: (0131 6)50 5749
Email: R.Cheung@ed.ac.uk |
Course secretary | Ms Kathryn Nicol
Tel: (0131 6)50 5687
Email: kathryn.nicol@ed.ac.uk |
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© Copyright 2011 The University of Edinburgh - 16 January 2012 6:03 am
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