Postgraduate Course: High Level Programming of Reconfigurable Hardware (MSc) (PGEE11062)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Course type | Standard |
Availability | Not available to visiting students |
| Credit level (Normal year taken) | SCQF Level 11 (Postgraduate) |
Credits | 20 |
| Home subject area | Postgrad (School of Engineering) |
Other subject area | None |
| Course website |
None |
Taught in Gaelic? | No |
| Course description | The aim of this course is to produce students who are capable of designing reconfigurable hardware (FPGAs) from a high level language. |
Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
|
Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
| Additional Costs | None |
Course Delivery Information
|
| Delivery period: 2011/12 Semester 2, Not available to visiting students (SS1)
|
WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Laboratory | Lab | 1-11 | 09:00 - 13:00 | | | | |
| First Class |
Week 1, Monday, 09:00 - 13:00, Zone: King's Buildings. Lab |
| Exam Information |
| Exam Diet |
Paper Name |
Hours:Minutes |
|
|
| Main Exam Diet S2 (April/May) | | 2:00 | | |
Summary of Intended Learning Outcomes
1.Knowledge and understanding of:
I. The role of Field Programmable Gate Arrays (FPGAs) as modern computing platforms;
II. A range of FPGA design flows including High Level Language (HLL) design flows.
2. Intellectual:
I. Ability to choose between different FPGA design techniques, use them to develop FPGA-based applications and evaluate the resulting implementations.
3. Practical:
I. Ability to use an HLL-based FPGA design suite to develop applications on FPGAs. |
Assessment Information
Written Examination: 50% Practicals: 50%
Four 3-hour lab sessions would be run in this course. Students will submit the work produced at the end of each session, which will be assessed. |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Not entered |
| Transferable skills |
Not entered |
| Reading list |
Not entered |
| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords | FPGAs, High Level Programming, Handel-C, Electronic System Level design |
Contacts
| Course organiser | Dr Khaled Benkrid
Tel: (0131 6)50 5682
Email: K.Benkrid@ed.ac.uk |
Course secretary | Mrs Laura Smith
Tel: (0131 6)50 5690
Email: laura.smith@ed.ac.uk |
|
© Copyright 2011 The University of Edinburgh - 16 January 2012 6:32 am
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