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DEGREE REGULATIONS & PROGRAMMES OF STUDY 2012/2013
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DRPS : Course Catalogue : School of Informatics : Informatics

Undergraduate Course: Computer Architecture (INFR09009)

Course Outline
SchoolSchool of Informatics CollegeCollege of Science and Engineering
Course typeStandard AvailabilityAvailable to all students
Credit level (Normal year taken)SCQF Level 9 (Year 3 Undergraduate) Credits10
Home subject areaInformatics Other subject areaNone
Course website http://www.inf.ed.ac.uk/teaching/courses/car Taught in Gaelic?No
Course descriptionComputer architecture is about optimising the design of computer hardware and software under constraints of time, cost and power consumption. Over the years, improvements intechnology and advances in computer architecture have resulted in huge increases in computer performance. This course examines the fundamentals of high-performance computer architecture and looks at how the interface between hardware and software (architecture and compiler) influences performance.
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Co-requisites
Prohibited Combinations Other requirements Successful completion of Year 2 of an Informatics Single or Combined Degree, or equivalent by permission of the School.
Additional Costs None
Information for Visiting Students
Pre-requisitesNone
Displayed in Visiting Students Prospectus?Yes
Course Delivery Information
Delivery period: 2012/13 Semester 2, Available to all students (SV1) Learn enabled:  No Quota:  None
Location Activity Description Weeks Monday Tuesday Wednesday Thursday Friday
CentralLecture1-11 10:00 - 10:50
CentralLecture1-11 10:00 - 10:50
First Class Week 1, Monday, 10:00 - 10:50, Zone: Central. D.01, Forrest Hill
Exam Information
Exam Diet Paper Name Hours:Minutes
Main Exam Diet S2 (April/May)2:00
Resit Exam Diet (August)2:00
Summary of Intended Learning Outcomes
1 - Describe the structure and operational characteristics of a pipelined microprocessor.
2 - Explain principles of: orthogonal instruction set design; pipeline hazards and interlocks; out of order execution; scoreboards and reservation stations and their use; branch prediction (both static and dynamic); and techniques (both software and hardware) for exploiting loop-level parallelism.
3 - Evaluate the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements.
4 - Explain the principle of memory locality and show how a memory hierarchy exploits the various forms of locality.
5 - Give an outline design of a memory hierarchy and specify reasonable parameters for each configuration point (capacity, associativity, block size, and write policies) at each level in the hierarchy.
6 - Describe the memory coherency issues involved when designing a multiprocessor system, and explain the behaviour of a typical cache coherency protocol.
Assessment Information
Written Examination 75
Assessed Assignments 25
Oral Presentations 0

Assessment
Two practical exercises.

If delivered in semester 1, this course will have an option for semester 1 only visiting undergraduate students, providing assessment prior to the end of the calendar year.
Special Arrangements
None
Additional Information
Academic description Not entered
Syllabus 1.Fundamentals
Performance evaluation methods and metrics, principles of high performance design, technology issues.

2.Processor Design
Instruction set classes, registers, memory addressing. Pipeline design, pipeline hazards & interlocks, out-of-order execution, scoreboards and reservation stations. Control prediction techniques and their exploitation. Techniques for exploting instruction- and loop-level parallelism.

3.Memory System Design
Memory hierarchies. Basic cache design and improvements. Main memory design and advanced organisations.

4.I/O
I/O interface. RAIDS. Buses.

5.Multiprocessors
Multiprocessor organisations. Cache coherence.

Relevant QAA Computing Curriculum Sections: Architecture
Transferable skills Not entered
Reading list J.L. Hennessy & D.A. Patterson, Computer Architecture: A Quantitative Approach (3e), Morgan Kaufmann Publishers Inc., 2003.
Study Abroad Not entered
Study Pattern Not entered
KeywordsNot entered
Contacts
Course organiserMr Vijayanand Nagarajan
Tel: (0131 6)51 3440
Email: vijay.nagarajan@ed.ac.uk
Course secretaryMrs Victoria Swann
Tel: (0131 6)51 7607
Email: Vicky.Swann@ed.ac.uk
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© Copyright 2012 The University of Edinburgh - 14 January 2013 4:08 am