Undergraduate Course: Computer Architecture (INFR09009)
|School||School of Informatics
||College||College of Science and Engineering
||Availability||Available to all students
|Credit level (Normal year taken)||SCQF Level 9 (Year 3 Undergraduate)
|Home subject area||Informatics
||Other subject area||None
||Taught in Gaelic?||No
|Course description||Computer architecture is about optimising the design of computer hardware and software under constraints of time, cost and power consumption. Over the years, improvements in technology and advances in computer architecture have resulted in huge increases in computer performance. This course examines the fundamentals of high-performance computer architecture and looks at how the interface between hardware and software (architecture and compiler) influences performance.
Entry Requirements (not applicable to Visiting Students)
||Other requirements|| This course is open to all Informatics students including those on joint degrees. For external students where this course is not listed in your DPT, please seek special permission from the course organiser.
|Additional Costs|| None
Information for Visiting Students
|Displayed in Visiting Students Prospectus?||Yes
Course Delivery Information
|Delivery period: 2013/14 Semester 2, Available to all students (SV1)
||Learn enabled: No
|Course Start Date
|Breakdown of Learning and Teaching activities (Further Info)
Lecture Hours 20,
Seminar/Tutorial Hours 8,
Summative Assessment Hours 2,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
|Breakdown of Assessment Methods (Further Info)
||Hours & Minutes
|Main Exam Diet S2 (April/May)||2:00|
|Resit Exam Diet (August)||2:00|
Summary of Intended Learning Outcomes
|1 - Demonstrate the ability to describe the structure and operational characteristics of a pipelined microprocessor.
2 - Demonstrate the ability to explain principles of: orthogonal instruction set design; pipeline hazards and interlocks; out of order execution; scoreboards and reservation stations and their use; branch prediction (both static and dynamic); and techniques (both software and hardware) for exploiting loop-level parallelism.
3 - Demonstrate the ability to quantitatively evaluate the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements.
4 - Demonstrate the ability to explain the principle of memory locality, to show how a memory hierarchy exploits the various forms of locality, and to analyze the performance of a memory hierarchy.
5 - Demonstrate the ability to design, in outline, a memory hierarchy, and to specify reasonable parameters for each configuration point (capacity, associativity, block size, and write policies) at each level in the hierarchy.
6 - Demonstrate an understanding of the memory coherency issues involved when designing a multiprocessor system, and to explain the behaviour of a typical cache coherency protocol.
|Written Examination 75|
Assessed Assignments 25
Oral Presentations 0
Two practical exercises.
If delivered in semester 1, this course will have an option for semester 1 only visiting undergraduate students, providing assessment prior to the end of the calendar year.
Performance evaluation methods and metrics, principles of high performance design, technology issues.
Instruction set classes, registers, memory addressing. Pipeline design, pipeline hazards & interlocks, out-of-order execution, scoreboards and reservation stations. Control prediction techniques and their exploitation. Techniques for exploting instruction- and loop-level parallelism.
3.Memory System Design
Memory hierarchies. Basic cache design and improvements. Main memory design and advanced organisations.
I/O interface. RAIDS. Buses.
Multiprocessor organisations. Cache coherence.
Relevant QAA Computing Curriculum Sections: Architecture
||J.L. Hennessy & D.A. Patterson, Computer Architecture: A Quantitative Approach (5e), Morgan Kaufmann Publishers Inc., 2011.
Timetabled Laboratories 0
Non-timetabled assessed assignments 25
Private Study/Other 49
|Course organiser||Mr Vijayanand Nagarajan
Tel: (0131 6)51 3440
|Course secretary||Miss Claire Edminson
Tel: (0131 6)51 7607
© Copyright 2013 The University of Edinburgh - 13 January 2014 4:26 am