Postgraduate Course: Digital Systems Laboratory A (MSc) (PGEE10017)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Course type | Standard |
Availability | Not available to visiting students |
| Credit level (Normal year taken) | SCQF Level 10 (Postgraduate) |
Credits | 10 |
| Home subject area | Postgrad (School of Engineering) |
Other subject area | None |
| Course website |
None |
Taught in Gaelic? | No |
| Course description | The aim of this lab course is to produce students who are capable of developing synchronous digital circuits from high level functional specifications and prototyping them on to FPGA hardware using a standard hardware description language. |
Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
|
Co-requisites | |
| Prohibited Combinations | |
Other requirements | Courses passed equivalent to Digital Systems Design 3 (ELEE09024). Knowledge and understanding of the basics of combinational and synchronous digital circuits. |
| Additional Costs | None |
Course Delivery Information
|
| Delivery period: 2013/14 Semester 1, Not available to visiting students (SS1)
|
Learn enabled: Yes |
Quota: None |
Web Timetable |
Web Timetable |
| Course Start Date |
16/09/2013 |
| Breakdown of Learning and Teaching activities (Further Info) |
Total Hours:
100
(
Supervised Practical/Workshop/Studio Hours 30,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
68 )
|
| Additional Notes |
|
| Breakdown of Assessment Methods (Further Info) |
Written Exam
0 %,
Coursework
100 %,
Practical Exam
0 %
|
| No Exam Information |
Summary of Intended Learning Outcomes
1. Knowledge and understanding of:
I. Combinatorial and sequential circuits and number of ways of designing them;
II. Basic and linked state machines and a number of ways of designing them;
III. The importance of modular design, and design for reuse;
IV. The importance of a structured circuit development flow including functional specification, design, simulation, synthesis, implementation and testing;
V. A standard hardware description language and how it can be used to capture digital circuit designs at different levels of abstraction.
2. Intellectual
I. Ability to use and choose between different techniques for digital circuit design and capture;
II. Ability to evaluate synthesis results and correlate them with the corresponding high level design and capture.
3. Practical
I. Ability to use a commercial digital circuit development tool suite to develop synchronous digital circuits and prototype them on to FPGA hardware.
|
Assessment Information
| 90% lab-based assessment: 5 Checkpoints in total, of equal weight (18% each) 10% Report |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Lab 1 - Week 2: "HelloWorld" and "HelloLotsofWorlds" modules
Lab 2 - Week 3: "HelloSynchronousWorld", "ShiftingTheWorld" and "ShiftingManyWorlds" modules
Lab 3 - Week 4: "CountingTheWorld" and "TimingTheWorld" modules
Lab 4 - Week 5: "DecodingTheWorld" module
Lab 5 - Week 6: "TimingTheWorldInDecimalNow" module
Lab 6 - Week 7: "ColouringTheWorld" module
Lab 7 - Week 8: "TheWorldofStateMachines" and "TheWorldofLinkedStateMachine" modules
Lab 8 - Week 9: "Snake" Game module 1
Lab 9 - Week 10: "Snake" Game module 2
Lab 10 ¿ Week 11: Final Assessment |
| Transferable skills |
Institution of Engineering and Technology Benchmarks:
Outcome E1, Theme F:
- Ability to use combinatorial and sequential logic circuits (Extensive)
There are dedicated lab sessions for combinatorial circuit design e.g. decoders, and sequential logic design e.g. registers and memories. These are demonstrated on real FPGA hardware in the labs through the generation of light patterns on LEDs, seven-segment LED displays etc.
- Ability to use VLSI systems and techniques (Moderate)
The lab is entirely FPGA based whereby students apply VLSI design techniques such as task scheduling and mapping onto FPGA fabric.
- Apply number systems as appropriateness in hardware systems (Extensive)
Fixed point arithmetic is used in the labs¿ FPGA designs with the minimum necessary word lengths calculated by students in order to meet data range requirements and minimise the resulting implementation logic area. - Analyse VLSI circuits to determine speed, area, power consumption, etc. (Moderate)
In the labs, the resulting FPGA implementations e.g. of a 7-segment display decoder, are analysed in terms of speed and area, and basic correlations between Verilog design capture and corresponding implementations are made.
Outcome E1, Theme G
- Demonstrate an understanding of Architecture and organisation (Moderate)
Introductory short lectures cover the basics of FPGA architectures. All labs target an FPGA platform.
- Demonstrate an understanding of fundamentals of programming and programming languages (Extensive)
Verilog is used in the labs for FPGA programming. The fundamentals of the Verilog language (lexicon, syntax and semantics) are covered in the labs.
Outcome E3, Theme F
- Use hierarchy, hardware description, and finite state design tools to represent a complex digital design (Extensive)
The labs culminate in the development of a ¿Snake¿ game on FPGA hardware. The latter consists of a hierarchy of reusable modules e.g. counters and decoders, controlled by linked state machine. Xilinx ISE tool is used for design capture in Verilog.
- Simulate at the functional and timing level to verify the correct working of a digital design (Extensive)
Xilinx ISE tool suite is used for functional simulation, mapping and routing, before FPGA bitstreams are downloaded on to FPGA boards for testing.
Outcome E4, Theme F
- Demonstrate an understanding of and an ability to apply top-down digital design methods in the synthesis of a digital system (Extensive)
In the labs, students are presented with a problem e.g. design of a 7-segment decoder, and asked to use Xilinx ISE tool to design an FPGA architecture for it, capture it in Verilog, simulate it functionally, synthesise it, and test it on real FPGA hardware.
NB. Students are given design and coding hints throughout. |
| Reading list |
Digital Design, An Embedded Systems Approach Using Verilog
By Peter J Ashenden, Morgan Kaufmann, 2007, ISBN-13: 978-0123695277 |
| Study Abroad |
Not entered |
| Study Pattern |
3-hour weekly labs over 10 weeks. Students build increasingly complex digital circuits (combinatorial and sequential) every week culminating in the development of a Snake Game on FPGA (captured in Verilog and implemented on a Digilent Basys 2 FPGA board). |
| Keywords | Digital Circuits, Sequential circuits, combinatorial circuits, synchronous circuits, Verilog, HDL, F |
Contacts
| Course organiser | Dr Alister Hamilton
Tel: (0131 6)50 5597
Email: Alister.Hamilton@ed.ac.uk |
Course secretary | Mrs Sharon Potter
Tel: (0131 6)51 7079
Email: Sharon.Potter@ed.ac.uk |
|
© Copyright 2013 The University of Edinburgh - 10 October 2013 5:00 am
|
University Homepage