Undergraduate Course: Digital Systems Laboratory 3 (ELEE09018)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 9 (Year 3 Undergraduate) |
Availability | Available to all students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | The aim of this lab course is to produce students who are
capable of developing synchronous digital circuits from high
level functional specifications and prototyping them on to
FPGA hardware using a standard hardware description
language. |
| Course description |
Lab 1 - Week 2: "HelloWorld" and "HelloLotsofWorlds" modules
Lab 2 - Week 3: "HelloSynchronousWorld" and "ShiftingTheWorld" modules
Lab 3 - Week 4: "ShiftingManyWorlds" and "CountingTheWorld" modules
Lab 4 - Week 5: "TimingTheWorld" module and assessment
Lab 5 - Week 6: "TimingTheWorldInDecimalNow" and "DecodingTheWorld" modules
Lab 6 - Week 7: "ColouringTheWorld" module and assessment
Lab 7 - Week 8: "TheWorldofStateMachines" module
Lab 8 - Week 9: "TheWorldofLinkedStateMachine" module and assessment
Lab 9 - Week 10: "Snake Game" module
Lab 10 - Week 11: "Snake Game" module and assessment
|
Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
|
Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
| Additional Costs | None - If possible, boards can be lent to student to use at home in exchange for a deposit to be paid back at the end of semester |
Information for Visiting Students
| Pre-requisites | Knowledge and understanding of the basics of combinational
and synchronous digital circuits |
Course Delivery Information
|
| Academic year 2014/15, Available to all students (SV1)
|
Quota: None |
| Course Start |
Semester 1 |
Timetable |
Timetable |
| Learning and Teaching activities (Further Info) |
Total Hours:
100
(
Formative Assessment Hours 1,
Summative Assessment Hours 10,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
87 )
|
| Assessment (Further Info) |
Written Exam
0 %,
Coursework
100 %,
Practical Exam
0 %
|
| Additional Information (Assessment) |
100% lab-based assessment: 4 Checkpoints in total, with weight of 20%, 25%, 25% and 30%. |
| Feedback |
Not entered |
| No Exam Information |
Learning Outcomes
1. Knowledge and understanding of:
I. Combinatorial and sequential circuits and number of ways of
designing them;
II. Basic and linked state machines and a number of ways of
designing them;
III. The importance of modular design, and design for reuse;
IV. The importance of a structured circuit development flow
including functional specification, design, simulation, synthesis,
implementation and testing;
V. A standard hardware description language and how it can
be used to capture digital circuit designs at different levels of
abstraction;
2. Intellectual
I. Ability to use and choose between different techniques for
digital circuit design and capture;
II. Ability to evaluate synthesis results and correlate them with
the corresponding high level design and capture;
3. Practical
I. Ability to use a commercial digital circuit development tool
suite to develop synchronous digital circuits and prototype
them on to FPGA hardware;
|
Reading List
Digital Design, An Embedded Systems Approach Using Verilog
By Peter J Ashenden, Morgan Kaufmann, 2007, ISBN-13: 978-
0123695277 |
Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | Digital Circuits, Sequential and combinatorial circuits, synchronous circuits and Verilog |
Contacts
| Course organiser | Dr Jiabin Jia
Tel: (0131 6)51 3568
Email: Jiabin.Jia@ed.ac.uk |
Course secretary | Mrs Lynn Hughieson
Tel: (0131 6)50 5687
Email: Lynn.Hughieson@ed.ac.uk |
|
© Copyright 2014 The University of Edinburgh - 12 January 2015 3:56 am
|
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