Postgraduate Course: Digital System Design (MSc) (PGEE10008)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 10 (Postgraduate) |
Availability | Not available to visiting students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | This course is lecture based and is taken by all students taking the MSc in Electronics in Semester 2. It comprises one 20 lecture module. The course aims to present the principles of design re-use in the context of System-on-Chip (SoC) technology. The design and selection of soft, firm, and hard IP blocks are considered. Emerging design practices and standards are reviewed. Two target technologies are addressed: deep-submicron ASICs and field programmable gate arrays (FPGAs). |
| Course description |
Not entered
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Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
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Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
Course Delivery Information
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| Academic year 2014/15, Not available to visiting students (SS1)
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Quota: None |
| Course Start |
Semester 2 |
Timetable |
Timetable |
| Learning and Teaching activities (Further Info) |
Total Hours:
100
(
Lecture Hours 20,
Seminar/Tutorial Hours 10,
Formative Assessment Hours 1,
Summative Assessment Hours 2,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
65 )
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| Assessment (Further Info) |
Written Exam
100 %,
Coursework
0 %,
Practical Exam
0 %
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| Additional Information (Assessment) |
Assessment will be based on a single written paper of 90 minutes duration. |
| Feedback |
Not entered |
| Exam Information |
| Exam Diet |
Paper Name |
Hours & Minutes |
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| Main Exam Diet S2 (April/May) | | 2:00 | |
Learning Outcomes
At the conclusion of this course students should be able to:
1. Understand architectural design and synthesis principles;
2. Understand the concept of Hardware Description Languages (HDLs);
3. Understand the transformation of an algorithm from specification to an RTL (described with a Hardware Description Language such as Verilog-HDL);
4. Understand the technological conditions behind the need for greater design re-use for IC systems;
5. Differentiate between the different types of intellectual property (IP) blocks, their advantages and disadvantages;
6. Evaluate the appropriateness of a particular IP block for a given application;
7. Assess a piece of soft IP using the QIP metric;
8. Assess a piece of soft IP using industrial tools such as DesignChecker;
9. Understand the generation of a Hard IP;
10. Apply the design guidelines for IP block authoring;
11. Understand the effects of DSM technology on the CAD flow for ASIC design;
12. Be familiar with the DSM ASIC design methodology;
13. Be familiar with general HDL coding guidelines for reuse;
14. Be familiar with low power design techniques;
15. Understand high level synthesis techniques for high performance implementations;
16. Understand advanced computer architectures;
17. Understand datapath architectures used for high performance implementations.
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Reading List
1. Computer Organisation and Design, The Hardware / Software Interface, Patterson & Hennesey, 4th Edition.
ISBN: 9780123747501
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Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | Not entered |
Contacts
| Course organiser | Dr Adam Stokes
Tel: (0131 6)50 5611
Email: Adam.Stokes@ed.ac.uk |
Course secretary | Mrs Sharon Potter
Tel: (0131 6)51 7079
Email: Sharon.Potter@ed.ac.uk |
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