Postgraduate Course: Sigma Delta Data Converters (MSc) (PGEE11114)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 11 (Postgraduate) |
Availability | Not available to visiting students |
| SCQF Credits | 20 |
ECTS Credits | 10 |
| Summary | This course will equip the student with an understanding of sigma-delta data converters at a theoretical and practical level. The coursework makes a link between the digital signal processing concepts of sigma delta conversion and implementation in integrated circuit hardware.
The course will briefly review the basics of discrete-time signals and systems, before looking at block diagrams and circuit implementations of modulator structures. Saturation, stability and limit cycle behaviour of modulator loops will be described and related to circuit structure. Non-ideal behaviour of modulators such as noise, matching, finite gain and settling will be related to circuit level implementations.
The course will be illustrated throughout with MATLAB, Simulink and Cadence Verilog A examples linking to laboratory sessions and a design exercise issued at the start of semester. |
| Course description |
Lecture 1: Reminder of the basics of discrete-time signals and
systems.
Topics include: sampling, aliasing, interpolation,
reconstruction, quantization modelled as noise, and the effects
of sampling jitter. General block diagram of oversampled
system (ADC and DAC, decimation and interpolation).
Frequency domain representation of signals and noise. Fourier
series, Fourier transforms and computer-based computational
techniques, including the Discrete Fourier Transform (DFT),
Fast Fourier Transform (FFT), windowing and coherent
sampling principles. Power spectral density (PSD). Averaging
to reduce quantisation noise. Sincx.
Lecture 2: The principles of delta-sigma modulation.
Principle of oversampling to reduce the effects of quantization
noise, followed by noise-shaping to enhance performance.
Block diagram of 1st order modulator. Time-domain model
using a first-order lowpass system then followed by a
frequency-domain description. Z-transfer function of NTF and
STF. In-band and filtered noise. Power of noise and signal,
SNR formula. Quantiser gain. Limit cycles, idle tones and
dither. Simulink examples.
Lecture 3: Second order modulators
Second-order modulator block diagrams. Z-transfer function of
NTF, STF. MASH implementation. Single loop implementation.
Comparison of 1st and 2nd order. Saturation. Dynamic range
scaling equalisation at internal nodes. Limit cycles. Formula of
SNR with modulator order and oversampling. Simulink
examples.
Lecture 4: Higher order modulators
Higher-order block diagram. Implmentation of higher order
modulator as MASH or single loop. Instability. General higher
order modulator. Placement of zeros in NTF.
Feedback/feedforward to improve THD. NTF comparison.
Bandpass. Improvement of stability by multibit quantisation
and feedback. Matlab SD toolbox for design.
Lecture 5: Sigma-delta DAC
Sigma-delta modulation in digital domain. DAC matching.
Multi-bit DAC. Mismatch effects on linearity. Randomised
selection of elements. Dynamic element matching (DEM). Data
weighted averaging (DWA). Tones. Tree DEM. Multi-bit
feedback in ADC. Switched capacitor output filter. kT/C noise.
Lecture 6: Circuit Implementation of Modulators
Switched capacitor implementation of 1st order and 2nd order.
DAC requirements. Half delay and feedthrough integrators,
settling. Choice of capacitor ratios. Dynamic range scaling
equalisation at internal nodes Differential/single ended.
Cadence Verilog A examples.
Lecture 7: Transistor Level Implementation of Modulators
OTA and Opamp implementations. Comparator
implementations. Gm-C modulators. Power consumption
optimisation.
Lecture 8: Non-ideal effects in Sigma-delta modulators
Matching, finite opamp gain, incomplete settling, 1/f and
thermal noise. Effect on MASH, single loop etc. Cadence
Verilog A examples.
Lecture 9: Digital filter implementation
Filter order choice related to loop order. Comb filters.
Reduction in sample frequency. Hardware requirements. Filter
transfer function design. FIR, IIR filter implementation. Raised
Cosine. Elliptic/Chebyshev. Decimation and interpolation filters.
Power consumption/gate area.
Lecture 10: Modulator Applications
Frequency synthesizers, audio recording, Class-D audio, high
frequency modulators. Multi-standard comms. Gm-C
implementations. State of the art (p358-359 Schreier)
Lecture 11: Guest lecture.
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Course Delivery Information
|
| Academic year 2014/15, Not available to visiting students (SS1)
|
Quota: None |
| Course Start |
Semester 2 |
Timetable |
Timetable |
| Learning and Teaching activities (Further Info) |
Total Hours:
200
(
Lecture Hours 10,
Seminar/Tutorial Hours 5,
Supervised Practical/Workshop/Studio Hours 30,
Formative Assessment Hours 1,
Summative Assessment Hours 12,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
138 )
|
| Assessment (Further Info) |
Written Exam
50 %,
Coursework
50 %,
Practical Exam
0 %
|
| Additional Information (Assessment) |
Coursework (50%) Exam (50%) |
| Feedback |
Not entered |
| Exam Information |
| Exam Diet |
Paper Name |
Hours & Minutes |
|
| Main Exam Diet S2 (April/May) | | 2:00 | |
Learning Outcomes
On completion of the course students will be able to:
1. understand the operating principles of sigma delta converters
2. choose the order, structure and coefficients of sigma delta modulators at a block level
3. employ SIMULINK and MATLAB to simulate and design the modulator coefficients
4. use Cadence to study non-ideal effects in modulators
5. propose circuit implementations of modulators
6. understand the range of applications of sigma-delta converters.
|
Reading List
Understanding Sigma-Delta Data Converters, Schreier and
Temes, IEEE Press, ISBN 978-0-471-46585-0 |
Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | Sigma-delta, delta-sigma, analogue to digital, digital to analogue, integrated circuits |
Contacts
| Course organiser | Dr Robert Henderson
Tel: (0131 6)50 5645
Email: Robert.Henderson@ed.ac.uk |
Course secretary | Mrs Sharon Potter
Tel: (0131 6)51 7079
Email: Sharon.Potter@ed.ac.uk |
|
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