Undergraduate Course: Digital System Design 3 (ELEE09024)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Course type | Standard |
Availability | Available to all students |
| Credit level (Normal year taken) | SCQF Level 9 (Year 3 Undergraduate) |
Credits | 10 |
| Home subject area | Electronics |
Other subject area | None |
| Course website |
None |
Taught in Gaelic? | No |
| Course description | This course is a lecture course and is taken by all students taking the third year of electronics and/or electrical engineering degree in Semester 1. It comprises one 22 lecture module.
Digital System Design 3 aims to build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for datapath and FSM design. |
Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
Students MUST have passed:
Digital System Design 2 (ELEE08015)
|
Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
| Additional Costs | None |
Information for Visiting Students
| Pre-requisites | Must have understanding and knowledge of: Boolean Algebra, logic gates, Combinational logic design, minimisation of combinational logic (e.g. Karnaugh Maps), basic sequential circuit design. |
| Displayed in Visiting Students Prospectus? | No |
Course Delivery Information
|
| Delivery period: 2014/15 Semester 1, Available to all students (SV1)
|
Learn enabled: Yes |
Quota: None |
|
Web Timetable |
Web Timetable |
| Course Start Date |
15/09/2014 |
| Breakdown of Learning and Teaching activities (Further Info) |
Total Hours:
100
(
Lecture Hours 22,
Seminar/Tutorial Hours 22,
Summative Assessment Hours 2,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
52 )
|
| Additional Notes |
|
| Breakdown of Assessment Methods (Further Info) |
Written Exam
100 %,
Coursework
0 %,
Practical Exam
0 %
|
| Exam Information |
| Exam Diet |
Paper Name |
Hours & Minutes |
|
| Main Exam Diet S1 (December) | | 2:00 | |
Summary of Intended Learning Outcomes
1.Understand the concept of synthesis and modern digital circuit design;
2.Understand the need for optimisation;
3.Understand the steps involved in synthesis and identify different types of circuits;
4.Understand design methodologies using current computer aided design tools;
5.Understand digital circuit representation formats including high level hardware description languages such as Verilog-HDL; 6.Understand the general digital circuit structure;
7.Understand the concept of static timing analysis with use of cell delay and wireload models;
8.Understand binary arithmetic, number representation and coding, including 2¿s complement and floating-point representations; 9.Understand the basic datapath structures, including adders and multipliers;
10.Design and analyse small synchronous digital circuits which incorporate D, T or JK Flip Flops;
11.Implement small synchronous circuit designs using discrete gates and flip-flops and programmable logic devices;
12.Understand synchronous flip-flops, setup and hold timing constraints;
13.Understand synchronous counters, non-binary synchronous counters, generalised small synchronous design methods;
14.Understand Moore and Mealy machines, sate diagrams, ASM charts; 15.Design synchronous sequence detectors;
16.Understand Programmable Logic Devices (PLDs). |
Assessment Information
| 100% written examination. |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Introduction to Digital System Design
Logic Synthesis
Deep Sub Micron (DSM) Issues
Datapaths
Binary arithmetic, Number representation and coding
2's complement representation, Floating point representation, ANSI/IEEE Floating Point Standard 754-1985, Binary Coded Decimal (BCD), Grey Code
Adders
Full adder, Ripple-carry adder, Carry-bypass adder, Carry-select adder, Square root carry-select adder, Carry-lookahead adder
Multipliers
Binary multiplication, Array multiplier, Carry-save multiplier, Tree multipliers, Wallace-Tree multiplier
Sequential Circuits
Introduction to sequential circuits
Definition of a sequential circuit, Definition of a synchronous circuit, asynchronous R-S flip-flop, State tables, master-slave J-K flip-flop, D and T type flip-flops, Setup and hold times
Basic Sequential Circuits - Counters
State Machines
Finite State Machines (FSMs), Moore and Mealy machines, State diagrams, ASM charts, Conventions for ASM charts, Synthesis from an ASM chart, Drawing timing diagrams from ASM charts
Reduction of State Tables
Sequential design implementations
Introduction to different implementation styles, Programmable and non-programmable implementations, PLAs and FPGAs, Design of sequential networks using ROMs and PLAs, Design of sequential networks using sequential PLAs |
| Transferable skills |
Not entered |
| Reading list |
Fundamentals of Logic Design: fourth edition, C. H. Roth, (West Publishing Company) 1992
Application-Specific Integrated Circuits, M.J.S. Smith, (Addison Wesley) 1997, ISBN 0 201 50022 1
Digital Integrated Circuits: A Design Perspective, J.M. Rabaey, Prentice Hall (1996), ISBN 0 13 1786091
HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL and Verilog, D.J. Smith, (Doone Publications) 1999, ISBN 0 9651934 3 8
The art of digital design, D. Winkel and F. Prosser, (Prentice hall) 1980 Electronic Logic Circuits, J.R. Gibson, (Edward Arnold) 1992 |
| Study Abroad |
Not entered |
| Study Pattern |
2 lectures per week for 11 weeks
1 tutorial per week for 10 weeks |
| Keywords | digital circuits, combinational logic, sequential logic, FSM, finite state machine, datapath, adder, |
Contacts
| Course organiser | Dr Alister Hamilton
Tel: (0131 6)50 5597
Email: Alister.Hamilton@ed.ac.uk |
Course secretary | Mrs Lynn Hughieson
Tel: (0131 6)50 5687
Email: Lynn.Hughieson@ed.ac.uk |
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