Postgraduate Course: Analogue VLSI B (ELEE11043)
|School||School of Engineering
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 11 (Postgraduate)
||Availability||Available to all students
|Summary||This course will extend the student's knowledge of analogue integrated circuit design to a variety of common blocks found in mixed-signal systems.
1.To extend the student's proficiency and understanding of the design flow for analogue and mixed-signal circuits using industry-standard computer-aided design tools.
2.To advance design knowledge of common analogue circuits used within mixed-signal systems.
3.To carry out a design project of an integrated circuit block from specifications to layout and verification using state-of-the-art CAD tools.
This course will prepare the student for work within a design team involving interaction between analogue and digital design engineers.
The lecture series covers all the concepts necessary to complete the design of a cyclic analogue to digital converter in a submicron CMOS technology. The practical work of the course involves the design from specifications to layout of a 200MHz GBW fully-differential amplifier in a foundry 0.35um CMOS process. The amplifier forms the core of a 10-bit cyclic ADC covered in the lecture material. Students employ Cadence mixed-signal design tools and gain a familiarity of the complete design flow from schematic capture, analogue simulation, worst-case and yield prediction, custom layout, verification and post-layout extraction. The course is assessed on the basis of a design report (85%) and an oral design review (15%) conducted at a workstation with the design database and report available.
The lecture course synopsys is as follows: cyclic ADC operation, ADC specifications, INL, DNL, SINAD, digital error correction, differential signals, fully-differential amplifiers, common-mode feedback, cascode biasing, power-down, settling, gain, phase, output swing requirements, transistor sizing methodology, switched-capacitor circuit operation, switches, charge injection, clock feedthrough, bottom plate sampling, latched-comparators, auto-zeroed comparators, voltage reference generation, timing generation, non-overlapping clock generators, ADC system operation and simulation techniques.
Entry Requirements (not applicable to Visiting Students)
|| Students MUST have passed:
Analogue VLSI A (ELEE11041)
||Other requirements|| None
Information for Visiting Students
|Pre-requisites||It is recommended that this course is taken along with Analogue VLSI A (ELEE11041)
|High Demand Course?
Course Delivery Information
|Academic year 2016/17, Available to all students (SV2)
|Learning and Teaching activities (Further Info)
Supervised Practical/Workshop/Studio Hours 70,
Formative Assessment Hours 1,
Summative Assessment Hours 20,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
||Assessment will be based on the following components of work:
1. Lab attendance
2. Record of design work
3. Design files (CAD data-base)
4. Design Report
5. Oral examination
|No Exam Information
| Students should:
1. Be familiar of a variety of building blocks and architectures found in mixed-signal integrated circuits such as ADC and DACs.
2. Be able to follow a computer-aided design flow for mixed-signal integrated circuits using industry-standard design tools
3. Be able to design, layout and verify analogue sub-blocks from the specification of a simple mixed-signal system.
|P.E. Allen and D. R. Holberg, CMOS Analog|
Circuit Design 2nd Edition, Oxford 2002,
ISBN 0-19-511 644-5
B. Razavi, Design of Analog CMOS
Integrated Circuits, McGraw-Hill, 2001, ISBN
A. Hastings, The Art of Analog Layout 2nd
Edition, Prentice-Hall 2006, ISBN 0-13-
|Graduate Attributes and Skills
|Keywords||VLSI circuits analogue
|Course organiser||Dr Robert Henderson
Tel: (0131 6)50 5645
|Course secretary||Miss Megan Inch
Tel: (0131 6)51 7079
© Copyright 2016 The University of Edinburgh - 3 February 2017 4:05 am