# DEGREE REGULATIONS & PROGRAMMES OF STUDY 2017/2018

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# Undergraduate Course: Digital System Design 3 (ELEE09024)

 School School of Engineering College College of Science and Engineering Credit level (Normal year taken) SCQF Level 9 (Year 3 Undergraduate) Availability Available to all students SCQF Credits 10 ECTS Credits 5 Summary This course is a lecture course and is taken by all students taking the third year of electronics and/or electrical engineering degree in Semester 1. It comprises one 22 lecture module. Digital System Design 3 aims to build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for datapath and FSM design. Course description Introduction to Digital System Design Logic Synthesis Deep Sub Micron (DSM) Issues Datapaths Binary arithmetic, Number representation and coding 2's complement representation, Floating point representation, ANSI/IEEE Floating Point Standard 754-1985, Binary Coded Decimal (BCD), Grey Code Adders Full adder, Ripple-carry adder, Carry-bypass adder, Carry-select adder, Square root carry-select adder, Carry-lookahead adder Multipliers Binary multiplication, Array multiplier, Carry-save multiplier, Tree multipliers, Wallace-Tree multiplier Sequential Circuits Introduction to sequential circuits Definition of a sequential circuit, Definition of a synchronous circuit, asynchronous R-S flip-flop, State tables, master-slave J-K flip-flop, D and T type flip-flops, Setup and hold times Basic Sequential Circuits - Counters State Machines Finite State Machines (FSMs), Moore and Mealy machines, State diagrams, ASM charts, Conventions for ASM charts, Synthesis from an ASM chart, Drawing timing diagrams from ASM charts Reduction of State Tables Sequential design implementations Introduction to different implementation styles, Programmable and non-programmable implementations, PLAs and FPGAs, Design of sequential networks using ROMs and PLAs, Design of sequential networks using sequential PLAs
 Pre-requisites Students MUST have passed: Digital System Design 2 (ELEE08015) Co-requisites Prohibited Combinations Students MUST NOT also be taking Analogue Circuits 3 (ELEE09026) AND Analogue Circuits and Digital System Design 3 (ELEE09033) Other requirements None Additional Costs None
 Pre-requisites Must have understanding and knowledge of: Boolean Algebra, logic gates, Combinational logic design, minimisation of combinational logic (e.g. Karnaugh Maps), basic sequential circuit design. High Demand Course? Yes
 Academic year 2017/18, Available to all students (SV1) Quota:  None Course Start Semester 1 Course Start Date 18/09/2017 Timetable Timetable Learning and Teaching activities (Further Info) Total Hours: 100 ( Lecture Hours 22, Seminar/Tutorial Hours 22, Formative Assessment Hours 1, Summative Assessment Hours 2, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 51 ) Assessment (Further Info) Written Exam 100 %, Coursework 0 %, Practical Exam 0 % Additional Information (Assessment) 100% written examination. Feedback Not entered Exam Information Exam Diet Paper Name Hours & Minutes Main Exam Diet S1 (December) 1:30 Resit Exam Diet (August) 1:30
 1.Understand the concept of synthesis and modern digital circuit design; 2.Understand the need for optimisation; 3.Understand the steps involved in synthesis and identify different types of circuits; 4.Understand design methodologies using current computer aided design tools; 5.Understand digital circuit representation formats including high level hardware description languages such as Verilog-HDL; 6.Understand the general digital circuit structure; 7.Understand the concept of static timing analysis with use of cell delay and wireload models; 8.Understand binary arithmetic, number representation and coding, including 2-s complement and floating-point representations; 9.Understand the basic datapath structures, including adders and multipliers; 10.Design and analyse small synchronous digital circuits which incorporate D, T or JK Flip Flops; 11.Implement small synchronous circuit designs using discrete gates and flip-flops and programmable logic devices; 12.Understand synchronous flip-flops, setup and hold timing constraints; 13.Understand synchronous counters, non-binary synchronous counters, generalised small synchronous design methods; 14.Understand Moore and Mealy machines, sate diagrams, ASM charts; 15.Design synchronous sequence detectors; 16.Understand Programmable Logic Devices (PLDs)and Field Programmable Gate Arrays (FPGAs).
 Digital Integrated Circuits: A Design Perspective, J.M. Rabaey, Prentice Hall (1996), ISBN 0 13 1786091 Digital Design (Verilog): An Embedded Systems Approach Using Verilog (26 Oct 2007)by Peter Ashenden (Author) FSM based Digital Design using Verilog HDL by Peter Minns and Ian Elliot Pub: Wiley (208) ISBN:978-0470-06070-4
 Graduate Attributes and Skills Not entered Special Arrangements None Keywords digital circuits,combinational logic,sequential logic,FSM,finite state machine,datapath,adder
 Course organiser Dr Alister Hamilton Tel: (0131 6)50 5597 Email: Alister.Hamilton@ed.ac.uk Course secretary Mrs Lynn Hughieson Tel: (0131 6)50 5687 Email: Lynn.Hughieson@ed.ac.uk
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