Undergraduate Course: Sigma Delta Data Converters 5 (ELEE11082)
|School||School of Engineering
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 11 (Year 5 Undergraduate)
||Availability||Available to all students
|Summary||This course will equip the student with an understanding of sigma-delta data converters at a theoretical and practical level. The coursework makes a link between the digital signal processing concepts of sigma delta conversion and implementation in integrated circuit hardware.
The course will briefly review the basics of discrete-time signals and systems, before looking at block diagrams and circuit implementations of modulator structures. Saturation, stability and limit cycle behaviour of modulator loops will be described and related to circuit structure. Non-ideal behaviour of modulators such as noise, matching, finite gain and settling will be related to circuit level implementations.
The course will be illustrated throughout with MATLAB, Simulink and Cadence Verilog A examples linking to laboratory sessions and a design exercise issued at the start of semester.
Reminder of the basics of discrete-time signals and systems.
Topics include: sampling, aliasing,interpolation, reconstruction, quantization modelled as noise, and the effects of sampling jitter. General block diagram of oversampled system (ADC and DAC, decimation and interpolation). Frequency domain representation of signals and noise. Fourier series, Fourier transforms and computer-based computational techniques, including the Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), windowing and coherent
sampling principles. Power spectral density (PSD). Averaging
to reduce quantisation noise.
The principles of delta-sigma modulation.
Principle of oversampling to reduce the effects of quantization noise, followed by noise-shaping to enhance performance. Block diagram of 1st order modulator. Time-domain model using a first-order lowpass system then followed by a frequency-domain description. Z-transfer function of NTF and
STF. In-band and filtered noise. Power of noise and signal,
SNR formula. Quantiser gain. Simulink examples.
First order modulator continued. Time domain simulation. Limit cycles, idle tones and dither. Dead zone. Simulink examples.
Second order modulators.
Second-order modulator block diagrams. Z-transfer function of NTF, STF. MASH implementation. Single loop implementation. Comparison of 1st and 2nd order. Saturation. Dynamic range scaling equalisation at internal nodes. Limit cycles. Formula of
SNR with modulator order and oversampling. Boser-Woolley, Silva-Steensgaard. Error feedback. Simulink examples.
Higher order modulators.
Higher-order block diagram. Implementation of higher order modulator as MASH or single loop. Instability. General higher order modulator. Placement of zeros in NTF. Feedback/feedforward to improve THD. NTF comparison. CIFF, CIFB, CRFF, CRFB structures. Matlab SD toolbox for design. Simulink examples.
Multi-bit feedback. Multi-bit quantisers. Effects on SQNR and stability. Simulink examples.
DAC matching effects in multi-bit DAC. Mismatch effects on modulator linearity. Randomised selection of elements. Dynamic element matching (DEM). Data weighted averaging (DWA). Tones. Tree DEM. Multi-bit feedback in ADC. Simulink examples.
Multi-stage modulators. 1+1+1, 2+1 MASH, SMASH. Stability. Error term generation. Simulink examples.
Circuit Implementation of Modulators.
Non overlapping clock generation.
Switched capacitor implementation of delaying and non-delaying integrators. Latched comparators. 2-level DAC implementation. First and second order switched capacitor modulator. Cadence examples.
Fully differential switched-capacitor modulators. Multi-bit quantiser and DAC implementation.
Switch resistance and transmission gate sizing. Amplifier and switch settling. Synamic range scaling. Cadence examples.
Noise sources. 1/f and thermal noise. kT/C noise in switched capacitor modulators. Capacitor sizing for noise. Total modulator noise. Cadence examples.
Information for Visiting Students
|High Demand Course?
Course Delivery Information
|Academic year 2017/18, Available to all students (SV1)
|Learning and Teaching activities (Further Info)
Lecture Hours 10,
Seminar/Tutorial Hours 5,
Supervised Practical/Workshop/Studio Hours 30,
Formative Assessment Hours 1,
Summative Assessment Hours 12,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
||Coursework (50%) Exam (50%)
||Hours & Minutes
|Main Exam Diet S2 (April/May)||2:00|
On completion of this course, the student will be able to:
- On completion of the course students will be able to: - understand the operating principles of sigma delta converters
- choose the order, structure and coefficients of sigma delta modulators at a block level -
- employ SIMULINK and MATLAB to simulate and design the modulator coefficients
- use Cadence to study non-ideal effects in modulators
- propose circuit implementations of modulators and understand the range of applications of sigma-delta converters.
|Understanding Sigma-Delta Data Converters, Schreier and|
Temes, IEEE Press, ISBN 978-0-471-46585-0
|Graduate Attributes and Skills
|Keywords||Sigma-delta,delta-sigma,analogue to digital,digital to analogue,integrated circuits
|Course organiser||Dr Robert Henderson
Tel: (0131 6)50 5645
|Course secretary||Miss Megan Inch
Tel: (0131 6)51 7079