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DRPS : Course Catalogue : School of Informatics : Informatics

Undergraduate Course: Computer Architecture (INFR09009)

Course Outline
SchoolSchool of Informatics CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 9 (Year 3 Undergraduate) AvailabilityAvailable to all students
SCQF Credits10 ECTS Credits5
SummaryComputer architecture is about optimising the design of computer hardware and software under constraints of time, cost and power consumption. Over the years, improvements in technology and advances in computer architecture have resulted in huge increases in computer performance. This course examines the fundamentals of high-performance computer architecture and looks at how the interface between hardware and software (architecture and compiler) influences performance.
Course description 1.Fundamentals
Performance evaluation methods and metrics, principles of high performance design, technology issues.

2.Processor Design
Instruction set classes, registers, memory addressing. Pipeline design, pipeline hazards & interlocks, out-of-order execution, scoreboards and reservation stations. Control prediction techniques and their exploitation. Techniques for exploting instruction- and loop-level parallelism.

3.Memory System Design
Memory hierarchies. Basic cache design and improvements. Main memory design and advanced organisations.

4.Introduction to Multiprocessors
Multiprocessor organisations. Cache coherence.

Relevant QAA Computing Curriculum Sections: Architecture
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Co-requisites
Prohibited Combinations Other requirements This course is open to all Informatics students including those on joint degrees. For external students where this course is not listed in your DPT, please seek special permission from the course organiser.
Information for Visiting Students
High Demand Course? Yes
Course Delivery Information
Academic year 2017/18, Available to all students (SV1) Quota:  None
Course Start Semester 2
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 100 ( Lecture Hours 20, Seminar/Tutorial Hours 8, Summative Assessment Hours 2, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 68 )
Assessment (Further Info) Written Exam 75 %, Coursework 25 %, Practical Exam 0 %
Additional Information (Assessment) Two practical exercises.

You should expect to spend approximately 25 hours on the coursework for this course.

If delivered in semester 1, this course will have an option for semester 1 only visiting undergraduate students, providing assessment prior to the end of the calendar year.
Feedback Not entered
Exam Information
Exam Diet Paper Name Hours & Minutes
Main Exam Diet S2 (April/May)2:00
Resit Exam Diet (August)2:00
Learning Outcomes
On completion of this course, the student will be able to:
  1. Demonstrate the ability to describe the structure and operational characteristics of a pipelined microprocessor, and to explain principles of: orthogonal instruction set design; pipeline hazards and interlocks; out of order execution; scoreboards and reservation stations and their use; branch prediction (both static and dynamic); and techniques (both software and hardware) for exploiting loop-level parallelism
  2. Demonstrate the ability to quantitatively evaluate the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements
  3. Demonstrate the ability to explain the principle of memory locality, to show how a memory hierarchy exploits the various forms of locality, and to analyze the performance of a memory hierarchy
  4. Demonstrate the ability to design, in outline, a memory hierarchy, and to specify reasonable parameters for each configuration point (capacity, associativity, block size, and write policies) at each level in the hierarchy
  5. Demonstrate an understanding of the memory coherency issues involved when designing a multiprocessor system, and to explain the behaviour of a typical cache coherency protocol
Reading List
J.L. Hennessy & D.A. Patterson, Computer Architecture: A Quantitative Approach (5e), Morgan Kaufmann Publishers Inc., 2011.
Additional Information
Course URL
Graduate Attributes and Skills Not entered
KeywordsNot entered
Course organiserDr Vijayanand Nagarajan
Tel: (0131 6)51 3440
Course secretaryMrs Victoria Swann
Tel: (0131 6)51 7607
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