Undergraduate Course: Computer Architecture and Design (INFR10076)
|School||School of Informatics
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 10 (Year 3 Undergraduate)
||Availability||Available to all students
|Summary||In this course you will learn how to design a computer and understand the performance characteristics of computers. You will first acquire a working knowledge of digital design, through the Verilog Hardware Description Language, along with a good theoretical grounding in the design of the key components of a microprocessor. You will have an opportunity to learn, both theoretically and practically, how the Quantitative Approach to computer architecture enables computer architects to analyse and optimize microprocessors to maximize performance. Along the way, you will spend time in the lab, designing real hardware, and later in the course you will apply your recently-acquired knowledge of quantitative computer architecture to analyse a simulated system and optimize its performance.
This new course presents a logical re-factoring of a sub-set of the material previously contained in the UG3 Computer Architecture and Computer Design courses. The aim of this course is to give students a comparatively deep understanding of computer architecture, to an intermediate level, together with a solid understanding of techniques used to design the logical building blocks from which a computer is constructed. We consider an intermediate level in computer architecture to extend up to the point where students have a good understanding of instruction set architecture, single-issue in-order pipelined execution of instructions, superscalar out-of-order execution, and the memory hierarchies required by those processors. Within a processor, we explore the principles and practice of arithmetic and logic unit design, of the caches from which memory hierarchies are constructed, and the memory and logic gate technologies from which computers are constructed. Throughout the course, there is a strong emphasis on the Quantitative Approach to computer architecture; this informs not only the theoretical topics but also the practical assignments, which always embody some element of the quantitative approach.
The philosophy of this course is that learning about computer architecture is particularly effective if reinforced by implementing key aspects of processor design, in real hardware when feasible, but also at higher levels of abstraction using simulated systems. This approach has been used very effectively in the previous Computer Design and Computer Architecture courses, and feedback often cites the value placed on the lab exercises by students.
Review of logic design and implementation technologies; from simple combinational logic to state machines for sequential circuits; logic design using Verilog and introduction to FPGAs.
Register Transfer Level design principles; registers, clocks, timing budgets, setup and hold margins, clock skew, clock-domain crossing and synchronization, metastability.
Quantitative computer architecture; performance evaluation methods and metrics, principles of high-performance design.
Instruction Set Architecture (ISA) design; instruction set classes, registers, memory addressing. RISC vs CISC, how the ISA supports high-level languages, quantitative approach to ISA design. Example ISAs (e.g. MIPS, RISC-V). ISA requirements for embedded systems.
Pipelined processor design; pipeline hazards and interlocks, control prediction techniques and their usage.
Out-of-order execution; scoreboards, reservation stations, register renaming, quantitative analysis of performance.
Computer Arithmetic and ALU Design
Introduction to binary arithmetic functions; fixed-point addition, subtraction, multiplication and division.
Advanced techniques in computer arithmetic; carry-look ahead adders, parallel-prefix adders, Booth-coded multipliers, Wallace and Dadda trees, sub-word parallelism, fractional fixed-point multiply- accumulate operations.
Floating-point computations; IEEE standard, floating-point addition and multiplication, high-performance fused-multiply-add architectures.
Memory System Design
Memory hierarchies; review of principles, quantitative analysis of memory hierarchy performance; exploring the design space of cache parameters.
Cache coherence in multi-core architectures; protocols and implementation techniques.
Main memory design; Interfacing between processor and memory, synchronous and asynchronous bus protocols.
Error detection and correction schemes; parity, Hamming codes, SECDED.
***This course replaces Computer Design (INFR09046) and Computer Architecture (INFR09009) FROM 2019/20.***
Entry Requirements (not applicable to Visiting Students)
|Prohibited Combinations|| Students MUST NOT also be taking
Digital System Design 4 (ELEE10007)
Students MUST NOT also be taking
Computer Architecture (INFR09009)
|Other requirements|| Students must not have taken Computer Architecture INFR09009 in academic session 2017/18.
Information for Visiting Students
|Pre-requisites||Course Title: Informatics 2C - Introduction to Computer Systems
Course Code: INFR08018
|High Demand Course?
Course Delivery Information
|Academic year 2019/20, Available to all students (SV1)
|Learning and Teaching activities (Further Info)
Lecture Hours 22,
Seminar/Tutorial Hours 4,
Supervised Practical/Workshop/Studio Hours 12,
Feedback/Feedforward Hours 4,
Summative Assessment Hours 53,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
Written Examination: 60%
Practical Examination: 0%
This course will be summatively assessed using a combination of written exam and laboratory-based coursework exercises. The coursework reinforces lecture-based teaching by setting tasks in which students design and implement some aspect of a microprocessor, both in real hardware and also at higher levels of abstraction, using simulated systems. Therefore, a higher than normal weighting is given to the coursework (40%), with the remainder of the assessment (60%) coming from a written exam. This follows the structure currently used in the Computer Design course. There will be no requirement to pass any individual element of the coursework.
The quantity of computer architecture/design lab-based coursework that can be reasonably accommodated in a single-semester 20-point has been established over the past two years in the CD course. This course aims to include the same quantity, but now taking account of the fact that there is a wider set of learning outcomes to achieve.
The coursework will comprise three individually assessed exercises, scheduled and sequenced to align with the delivery of theoretical material in lectures. The first two exercises will be carried out in the computer design lab, and will involve:
a) An introduction to the Xilinx FPGA system, followed by simple exercises in designing, implementing and testing combinational and synchronous digital systems on FPGA using Verilog.
b) A more complex computer design exercise, which will typically involve designing some type of arithmetic circuit, and analysing its area and timing on silicon. We hope to have infrastructure in place for 2019 that will allow students to integrate their arithmetic design into an existing microprocessor, and thereby experience a very realistic design scenario (while keeping it all feasible for an undergraduate exercise).
The third assignment will be a simulation-based computer architecture exercise, based on the style of exercises previously set in the CAR course. This could be one of the following:
c) Design and implement a simulated branch predictor and evaluate its effectiveness on program traces supplied to the student.
d) Using a supplied cache simulator, explore the design space of cache hierarchies under a defined set of design constraints, with the aim of finding an optimum cache configuration.
The marks given, and time allocated, for each coursework assignment will be proportionate to the level of difficulty and expected effort involved in each assignment. The allocation of coursework marks will be 10%, 40%, and 50% for assignments 1, 2 and 3 respectively.
||In this course, we propose a combination of mechanisms, including: feedforward during lab sessions, feedback on exercise sheet solutions during scheduled feedback sessions (in the first half of the course), and feedforward/feedback through tutorials (in the second half of the course). During the weekly tutorials, students would typically work through exam-like questions, and receive individual feedback. Students will be provided with feedforward during the lab sessions, involving lecturer and demonstrators discussing work with class members, with the aim of improving their skills as they develop their coursework solutions prior to hand-in. There will also ad hoc feedback sessions, in which the lecturer will give feedback to students on their exercise sheet solutions, and work through the solutions in an informal setting.
||Hours & Minutes
|Main Exam Diet S1 (December)||2:00|
|Resit Exam Diet (August)||2:00|
On completion of this course, the student will be able to:
- Describe the structure and operating characteristics of a high-performance microprocessor, and explain the principles of: orthogonal instruction set design; pipeline hazards and interlocks; branch prediction (both static and dynamic); out-of-order execution.
- Explain the design and operating principles of arithmetic units including: high-speed adders and multipliers; dividers; and floating-point units. And also demonstrate how selected fixed-point arithmetic functions can be implemented (in a laboratory setting).
- Design and implement both combinational and synchronous digital systems using state-of-the-art FPGA design tools and hardware description languages.
- Describe the structure and operating characteristics of memory systems; demonstrate the ability to evaluate quantitatively the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements; describe the operating principles of error detection and correction techniques applied to memory systems, and design a SECDED solution for a given memory system.
- Reason about the ways in which memory hierarchies can be configured to exploit locality in order to reduce average memory access times, and quantitatively evaluate the impact of varying cache design parameters (e.g. capacity, associativity, block size, and write policies) on performance; understand the operating principles of cache coherency protocols, and be able to compare and contrast different implementation techniques.
|Textbooks - Students are strongly recommended to purchase either  or , and one from [2, 3, 4].|
1. Hennessy/Patterson, Computer Architecture: A Quantitative Approach (5/e or 4/e).
2. Morris Mano, Michael D. Ciletti: Digital Design, 4/e, Prentice Hall, 2007.
3. Hamacher/Vranesic/Zaky: Computer Organization, McGraw-Hill, 2001.
4. Mano/Kime: Logic and Computer Design Fundamentals, Pearson, 2008.
5. Patterson/Hennessy: Computer Organization and Design, Elsevier, 2005.
6. Null/Lobur: The Essentials of Computer Organization and Architecture, Jones and Bartlett Publishers, 2003.
|Graduate Attributes and Skills
|| Students completing this course can be expected to have developed the following personal and professional attributes and skills, beyond the study of the subject itself:
The ability to exercise autonomy and initiative
Advanced skills in the field of quantitative analysis of complex digital systems
A working knowledge of how to optimize the performance of a system, using quantitative methods
A specific understanding of the industrial design processes involved in microprocessor development, and a broad understanding of the ASIC and IP businesses as delivery vehicles for digital devices
Practical skills in the design, implementation and testing of real-world digital designs, using a design flow of similar structure to that used today in industry
The ability to demonstrate originality and creativity in dealing with professional level issues
The ability to communicate effectively on a professional level with peers, senior colleagues and specialists
|Keywords||Computer Design,Computer Architecture,Computer Systems,CARD
|Course organiser||Prof Nigel Topham
Tel: (0131 6)50 5122
|Course secretary||Mrs Michelle Bain
Tel: (0131 6)51 7607