Postgraduate Course: HPC Architectures (INFR11175)
|School||School of Informatics
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 11 (Postgraduate)
||Availability||Available to all students
|Summary||After taking this course students should have a good understanding (from the practioner's perspective) of the way High Performance Computing (HPC) systems are designed and how this affects both the way they are programmed and the performance of applications.
The course will cover the following topics:
- Basic components of HPC systems: processors, memory, interconnect, storage.
- Classification of architectures: SIMD/MIMD, shared vs distributed memory, clusters
- System software: OSs, processes, threads, scheduling, batch systems.
- Brief history of HPC systems, including Moore's Law.
- CPU design: functional units, instructions sets, pipelining, branch prediction, ILP (superscalar, VLIW, SIMD instructions), multithreading.
- Caches: operation and design features
- Memory: operation and design features, including cache coherency and consistency
- Multicore CPUs, including cache and memory hierarchy
- GPGPUs: operation and design features
- Interconnects: operation and design features
- Current HPC architectures
Lectures will be followed by tutored practical sessions illustrating the key concepts.
Entry Requirements (not applicable to Visiting Students)
|Prohibited Combinations|| Students MUST NOT also be taking
Parallel Architectures (Level 11) (INFR11024)
||Other requirements|| Some practical exercises would benefit from familiarity with a programming language (such as Fortran or C).
Information for Visiting Students
|Pre-requisites||Some practical exercises would benefit from familiarity with a programming language (such as Fortran or C).
|High Demand Course?
Course Delivery Information
|Academic year 2019/20, Available to all students (SV1)
|Learning and Teaching activities (Further Info)
Lecture Hours 20,
Supervised Practical/Workshop/Studio Hours 8,
Summative Assessment Hours 2,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
||Written Exam 100 %
100% examination consisting of a two hour exam
||Via practical class exercises and on the exam.
||Hours & Minutes
|Main Exam Diet S1 (December)||HPC Architectures||2:00|
On completion of this course, the student will be able to:
- Understand the key components of HPC architectures
- Understand the basic principles of operation of these components
- Appreciate the main design choices and trade-offs in HPC architecture.
- Understand how the components are put together to form complete systems
- Understand how HPC system software is used to manage the hardware.
|Provided via Learn|
|Graduate Attributes and Skills
||Solution Exploration, Evaluation and Prioritisation.
Communication of complex ideas in accessible language
Working in an interdisciplinary field
Programming and Scripting
||There are limited spaces on this course. Students not on the MSc in High Performance Computing or MSc High Performance Computing with Data Science should contact the course secretary to confirm availability and confirm that they have the required prerequisites before being enrolled on the course.
The course is available to PhD students for class-only study. PhD students requiring a form of assessment (e.g. SUPA/School of Physics and Astronomy CDT students) must contact the course secretary to confirm method of enrolment.
|Additional Class Delivery Information
||2x lectures per week (Weeks 1-10), 1x Practical per week (Weeks 1, 3-7, 9, 11)
|Keywords||Computer Architectures,HPC,HPCA,HA,EPCC,High Performance Computing,Parallelism,Parallel
|Course organiser||Dr Darren White
Tel: (01316)51 3415
|Course secretary||Mr Ben Morse
Tel: (0131 6)51 3398