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DRPS : Course Catalogue : School of Informatics : Informatics

Postgraduate Course: HPC Architectures (INFR11175)

Course Outline
SchoolSchool of Informatics CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 11 (Postgraduate) AvailabilityAvailable to all students
SCQF Credits10 ECTS Credits5
SummaryAfter taking this course students should have a good understanding (from the practioner's perspective) of the way High Performance Computing (HPC) systems are designed and how this affects both the way they are programmed and the performance of applications.
Course description The course will cover the following topics:

- Basic components of HPC systems: processors, memory, interconnect, storage.
- Classification of architectures: SIMD/MIMD, shared vs distributed memory, clusters
- System software: OSs, processes, threads, scheduling, batch systems.
- Brief history of HPC systems, including Moore's Law.
- CPU design: functional units, instructions sets, pipelining, branch prediction, ILP (superscalar, VLIW, SIMD instructions), multithreading.
- Caches: operation and design features
- Memory: operation and design features, including cache coherency and consistency
- Multicore CPUs, including cache and memory hierarchy
- GPGPUs: operation and design features
- Interconnects: operation and design features
- Current HPC architectures

Lectures will be followed by tutored practical sessions illustrating the key concepts.
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Co-requisites
Prohibited Combinations Students MUST NOT also be taking Parallel Architectures (Level 11) (INFR11024)
Other requirements Some practical exercises would benefit from familiarity with a programming language (such as Fortran or C).
Information for Visiting Students
Pre-requisitesSome practical exercises would benefit from familiarity with a programming language (such as Fortran or C).
High Demand Course? Yes
Course Delivery Information
Academic year 2020/21, Available to all students (SV1) Quota:  80
Course Start Semester 1
Course Start Date 21/09/2020
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 100 ( Lecture Hours 20, Supervised Practical/Workshop/Studio Hours 8, Summative Assessment Hours 2, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 68 )
Assessment (Further Info) Written Exam 75 %, Coursework 25 %, Practical Exam 0 %
Additional Information (Assessment) Written Exam 75%
Coursework (Class test) 25%

Written examination comprised of 3 compulsory questions (equally weighted).

Coursework (class test) is an examination question presented to the students mid-Semester. This will be undertaken in time-limited conditions similar to an exam but during the course and providing students a mid-Semester opportunity to judge their progress and identify (with the help of feedback)
Feedback Via practical class exercises, coursework and on the exam.
Exam Information
Exam Diet Paper Name Hours & Minutes
Main Exam Diet S1 (December)HPC Architectures2:00
Learning Outcomes
On completion of this course, the student will be able to:
  1. Understand the key components of HPC architectures
  2. Understand the basic principles of operation of these components
  3. Appreciate the main design choices and trade-offs in HPC architecture.
  4. Understand how the components are put together to form complete systems
  5. Understand how HPC system software is used to manage the hardware.
Reading List
Provided via Learn
Additional Information
Graduate Attributes and Skills Solution Exploration, Evaluation and Prioritisation.
Critical thinking
Communication of complex ideas in accessible language
Working in an interdisciplinary field
Programming and Scripting
Special Arrangements There are limited spaces on this course. Students not on the MSc in High Performance Computing or MSc High Performance Computing with Data Science should contact the course secretary to confirm availability and confirm that they have the required prerequisites before being enrolled on the course.

The course is available to PhD students for class-only study. PhD students requiring a form of assessment must contact the course secretary to confirm method of enrolment.
Additional Class Delivery Information 2x lectures per week (Weeks 1-11), 1x Practical per week (most weeks during Semester)
KeywordsComputer Architectures,HPC,HPCA,HA,EPCC,High Performance Computing,Parallelism,Parallel
Course organiserDr Darren White
Tel: (01316)51 3415
Course secretaryMiss Jemma Auns
Tel: (0131 6)51 3545
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