Postgraduate Course: Data Converter Design in Simulink (MSc) (PGEE11200)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 11 (Postgraduate) |
Availability | Available to all students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | This course will equip the student with an understanding of sigma-delta data converters using theoretical analysis and high level macromodel simulation.
The course will briefly review the basics of discrete-time signals and systems, before looking at block diagrams and signal flow graph implementations of modulator structures. Saturation, stability and limit cycle behaviour of modulator loops will be described and related to circuit structure.
The course will be illustrated throughout with MATLAB, Simulink examples linking to laboratory sessions and a design exercise issued at the start of semester. |
| Course description |
Lecture 1:
Reminder of the basics of discrete-time signals and systems.
Topics include: sampling, aliasing,interpolation, reconstruction, quantization modelled as noise, and the effects of sampling jitter. General block diagram of oversampled system (ADC and DAC, decimation and interpolation). Frequency domain representation of signals and noise. Fourier series, Fourier transforms and computer-based computational techniques, including the Discrete Fourier Transform (DFT), Fast Fourier Transform (FFT), windowing and coherent
sampling principles. Power spectral density (PSD). Averaging
to reduce quantisation noise.
The principles of delta-sigma modulation.
Principle of oversampling to reduce the effects of quantization noise, followed by noise-shaping to enhance performance. Block diagram of 1st order modulator. Time-domain model using a first-order lowpass system then followed by a frequency-domain description. Z-transfer function of NTF and
STF. In-band and filtered noise. Power of noise and signal,
SNR formula. Quantiser gain. Simulink examples.
Lecture 2:
First order modulator continued. Time domain simulation. Limit cycles, idle tones and dither. Dead zone. Simulink examples.
Lecture 3:
Second order modulators.
Second-order modulator block diagrams. Z-transfer function of NTF, STF. MASH implementation. Single loop implementation. Comparison of 1st and 2nd order. Saturation. Dynamic range scaling equalisation at internal nodes. Limit cycles. Formula of
SNR with modulator order and oversampling. Boser-Woolley, Silva-Steensgaard. Error feedback. Simulink examples.
Lecture 4:
Higher order modulators.
Higher-order block diagram. Implementation of higher order modulator as MASH or single loop. Instability. General higher order modulator. Placement of zeros in NTF. Feedback/feedforward to improve THD. NTF comparison. CIFF, CIFB, CRFF, CRFB structures. Matlab SD toolbox for design. Simulink examples.
Lecture 5:
Multi-bit feedback. Multi-bit quantisers. Effects on SQNR and stability. Simulink examples.
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Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
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Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
Information for Visiting Students
| Pre-requisites | None |
Course Delivery Information
| Not being delivered |
Learning Outcomes
On completion of this course, the student will be able to:
- Understand the operating principles of sigma delta converters
- Choose the order, structure and coefficients of sigma delta modulators at a block level
- Employ SIMULINK and MATLAB to simulate and design the modulator coefficients
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Reading List
Understanding Sigma-Delta Data Converters, Schreier and
Temes, IEEE Press, ISBN 978-0-471-46585-0 |
Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | Not entered |
Contacts
| Course organiser | Dr Robert Henderson
Tel: (0131 6)50 5645
Email: Robert.Henderson@ed.ac.uk |
Course secretary | Mrs Megan Inch-Kellingray
Tel: (0131 6)51 7079
Email: M.Inch@ed.ac.uk |
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