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DRPS : Course Catalogue : School of Engineering : Electronics

Undergraduate Course: Digital System Design 3 (ELEE09024)

Course Outline
SchoolSchool of Engineering CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 9 (Year 3 Undergraduate) AvailabilityAvailable to all students
SCQF Credits10 ECTS Credits5
SummaryThis course is a lecture course and is taken by all students taking the third year of electronics and/or electrical engineering degree in Semester 1. It comprises one 22 lecture module.

Digital System Design 3 aims to build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for datapath and FSM design.
Course description Logic design fundamentals. State machines, equivalent states and state reduction. Implication
Introduction to hardware description languages (HDL). Synthesis. Behavioural, structural and data
flow (register-transfer level, RTL) models.
Programmable logic devices. Simple programmable logic devices, complex programmable logic
devices, field programmable gate arrays, programmable SoCs.
Design Examples. Data path, controller model.
Adders. Critical path, carry-lookahead adder, parallel prefix adder.
Multipliers. Add and shift multiplier, array multiplier. Signed integer/fraction multiplier.
State machine charts. Microprogramming.
Designing with FPGAs. Shannon┬┐s decomposition. Carry chains. Cascade chains. Dedicated
multipliers. Dedicated memory. Cost of programmability. Design translation (Synthesis). Mapping,
placement and routing.
Floating point arithmetic. Multiplication and addition.
Verification of digital systems. Functional verification. Timing verification.
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Students MUST have passed: Digital System Design 2 (ELEE08015)
Prohibited Combinations Students MUST NOT also be taking Digital System Design and Digital Systems Laboratory 3 (ELEE09035) OR Digital Systems Laboratory 3 (ELEE09018)
Other requirements None
Additional Costs None
Information for Visiting Students
Pre-requisitesMust have understanding and knowledge of: Boolean Algebra, logic gates, Combinational logic design, minimisation of combinational logic (e.g. Karnaugh Maps), basic sequential circuit design.
High Demand Course? Yes
Course Delivery Information
Academic year 2021/22, Available to all students (SV1) Quota:  None
Course Start Semester 1
Course Start Date 20/09/2021
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 100 ( Lecture Hours 22, Seminar/Tutorial Hours 22, Formative Assessment Hours 1, Summative Assessment Hours 2, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 51 )
Assessment (Further Info) Written Exam 100 %, Coursework 0 %, Practical Exam 0 %
Additional Information (Assessment) 100% written examination.
Feedback Not entered
Exam Information
Exam Diet Paper Name Hours & Minutes
Main Exam Diet S1 (December)1:30
Resit Exam Diet (August)1:30
Learning Outcomes
On completion of this course, the student will be able to:
  1. Understand the concept of synthesis and modern digital circuit design using hardware description languages (HDL)
  2. Understand basic datapath structures, including adder and multiplier architectures
  3. Under the design of combinational and sequential logic systems including finite state machines and state reduction
Reading List
Digital Systems Design Using VHDL, 3rd (international) edition, Charles H. Roth, Jr. and Lizy Kurian John. Publisher: Cengage Learning ISBN-13: 978-1-305-63892-1
ISBN-10: 1-305-63892-1

Digital Design (Verilog): An Embedded Systems Approach Using Verilog (26 Oct 2007)by Peter Ashenden (Author)

FSM based Digital Design using Verilog HDL by Peter Minns and Ian Elliot
Pub: Wiley (208)
Additional Information
Graduate Attributes and Skills Not entered
Special Arrangements None
Keywordsdigital circuits,combinational logic,sequential logic,FSM,finite state machine,datapath,adder
Course organiserDr Alister Hamilton
Tel: (0131 6)50 5597
Course secretaryMrs Lynn Hughieson
Tel: (0131 6)50 5687
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