Postgraduate Course: Parallel Architectures (Level 11) (INFR11024)
Course Outline
| School | School of Informatics |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 11 (Year 4 Undergraduate) |
Availability | Available to all students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | The aims of this course are threefold: (a) to investigate the various forms of parallelism found in uniprocessors and in multiprocessor and multicomputer systems; (b) to explore the issues which arise in these systems in terms of: (i) ensuring that programs are executed correctly by the hardware; (ii) maximising performance (c) to undertake an in-depth investigation of a specific area of current research in parallel architecture. |
| Course description |
* Introduction
Parallelism and Performance
Parallelism in Software
* Uniprocessor Parallelism
Vector & SIMD Instructions
Superscalar and VLIW processors
* Interconnection networks
Introduction
Routing Functions
Static Networks
Dynamic Networks
Combining Networks
* Multiprocessor & Multicomputer Systems
Introduction
Shared Memory Systems
Directory-based Coherence Protocols
Memory Consistency
NUMA Systems
Message Passing Systems
*Performance & Scalability
Performance metrics
Scalability
Relevant QAA Computing Curriculum Sections: Architecture, Simulation and Modelling
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Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
It is RECOMMENDED that students have passed
Informatics 2C - Introduction to Computer Systems (INFR08018) OR
Informatics 2C - Introduction to Computer Systems (INFR08027)
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Co-requisites | |
| Prohibited Combinations | |
Other requirements | This course is open to all Informatics students including those on joint degrees. For external students where this course is not listed in your DPT, please seek special permission from the course organiser.
Basic level of programming is assumed and not covered in lectures. The assessed assignment will involve programming.
It is recommended that students have a basic understanding of processor design and cache/memory hierarchies. The relevant material is available as part of the INF2C-CS course under (a) Processor design: single cycle and multicycle and (b) Memory hierarchy and caches. |
Information for Visiting Students
| Pre-requisites | None |
| High Demand Course? |
Yes |
Course Delivery Information
| Not being delivered |
Learning Outcomes
On completion of this course, the student will be able to:
- Describe the various forms of parallelism found in modern computer systems and the techniques used (a) to ensure that programs are executed correctly by parallel hardware (b) to maximise performance.
- Assess the effectiveness of techniques used to enhance the performance of computer systems.
- Record observations of on-line experiments, present this information in a variety of formats and draw conclusions from it.
- Investigate, explain and comment critically on a specific area of current parallel computer architecture research.
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Reading List
* D.E. Culler & J.P. Singh, Parallel Computer Architecture, Morgan Kaufmann, 1999.
* J.L. Hennessey & D.A. Patterson, Computer Architecture: a Quantitative Approach, 4th Edition, Morgan Kaufmann, 2006.
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Contacts
| Course organiser | Dr Vijayanand Nagarajan
Tel: (0131 6)51 3440
Email: vijay.nagarajan@ed.ac.uk |
Course secretary | Miss Lori Anderson
Tel: (0131 6)51 4164
Email: lori.anderson@ed.ac.uk |
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