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DRPS : Course Catalogue : School of Engineering : Electronics

Undergraduate Course: Data Converter Design in Cadence 5 (ELEE11106)

Course Outline
SchoolSchool of Engineering CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 11 (Year 5 Undergraduate) AvailabilityAvailable to all students
SCQF Credits10 ECTS Credits5
SummaryThis course will equip the student with an understanding of sigma-delta data converters at a practical circuit level. The coursework makes a link between the digital signal processing concepts of sigma delta conversion and implementation in integrated circuit hardware.

Saturation, stability and limit cycle behaviour of modulator loops will be described and related to circuit structure. Non-ideal behaviour of modulators such as noise, matching, finite gain and settling will be related to circuit level implementations.

The course will be illustrated throughout with MATLAB, Simulink and Cadence examples linking to laboratory sessions and a design exercise issued at the start of the course.
Course description Lecture 1:
DAC matching effects in multi-bit DAC. Mismatch effects on modulator linearity. Randomised selection of elements. Dynamic element matching (DEM). Data weighted averaging (DWA). Tones. Tree DEM. Multi-bit feedback in ADC. Simulink examples.

Lecture 2:
Multi-stage modulators. 1+1+1, 2+1 MASH, SMASH. Stability. Error term generation. Simulink examples.

Lecture 3:
Circuit Implementation of Modulators.
Non overlapping clock generation.
Switched capacitor implementation of delaying and non-delaying integrators. Latched comparators. 2-level DAC implementation. First and second order switched capacitor modulator. Cadence examples.

Lecture 4:
Fully differential switched-capacitor modulators. Multi-bit quantiser and DAC implementation.
Switch resistance and transmission gate sizing. Amplifier and switch settling. Synamic range scaling. Cadence examples.

Lecture 5:
Noise sources. 1/f and thermal noise. kT/C noise in switched capacitor modulators. Capacitor sizing for noise. Total modulator noise. Cadence examples.

Lecture 6:
Guest lecture
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Co-requisites Students MUST also take: Data Converter Design in Simulink 5 (ELEE11107)
Prohibited Combinations Other requirements None
Information for Visiting Students
High Demand Course? Yes
Course Delivery Information
Academic year 2023/24, Available to all students (SV1) Quota:  None
Course Start Blocks 4-5 (Sem 2)
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 100 ( Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 98 )
Assessment (Further Info) Written Exam 0 %, Coursework 100 %, Practical Exam 0 %
Additional Information (Assessment) Coursework: 100%
Feedback Not entered
No Exam Information
Learning Outcomes
On completion of this course, the student will be able to:
  1. Predict non-ideal circuit behaviour of modulators with SIMULINK and MATLAB;
  2. Use Cadence Design Systems software to study non-ideal effects in switched-capacitor modulator implementations;
  3. Propose circuit implementations of modulators and choose circuit component values to optimise performance.
Reading List
Understanding Sigma-Delta Data Converters, Schreier and Temes, IEEE Press, ISBN 978-0-471-46585-0
Additional Information
Graduate Attributes and Skills Not entered
KeywordsNot entered
Course organiserDr Robert Henderson
Tel: (0131 6)50 5645
Course secretaryMs Brunori Viola
Tel: (0131 6)50 5687
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