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DRPS : Course Catalogue : School of Informatics : Informatics

Undergraduate Course: Computer Architecture and Design (INFR10076)

Course Outline
SchoolSchool of Informatics CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 10 (Year 3 Undergraduate) AvailabilityAvailable to all students
SCQF Credits20 ECTS Credits10
SummaryIn this course you will learn how to design a computer and understand the performance characteristics of computers. You will first acquire a working knowledge of digital design, through the Verilog Hardware Description Language, along with a good theoretical grounding in the design of the key components of a microprocessor. You will have an opportunity to learn, both theoretically and practically, how the Quantitative Approach to computer architecture enables computer architects to analyse and optimize microprocessors to maximize performance. Along the way you will design real hardware, and later in the course you will apply your recently-acquired knowledge of quantitative computer architecture to analyse a simulated system and optimize its performance.
Course description The aim of this course is to give students a comparatively deep understanding of computer architecture, to an intermediate level, together with a solid understanding of techniques used to design the logical building blocks from which a computer is constructed. We consider an intermediate level in computer architecture to extend up to the point where students have a good understanding of instruction set architecture, single-issue in-order pipelined execution of instructions, superscalar out-of-order execution, and the memory hierarchies required by those processors. Within a processor, we explore the principles and practice of arithmetic and logic unit design, of the caches from which memory hierarchies are constructed, and the memory and logic gate technologies from which computers are constructed. Throughout the course, there is a strong emphasis on the Quantitative Approach to computer architecture; this informs not only the theoretical topics but also the practical assignments, which always embody some element of the quantitative approach.

The philosophy of this course is that learning about computer architecture is particularly effective if reinforced by implementing key aspects of processor design, in real hardware when feasible, but also at higher levels of abstraction using simulated systems. This approach has been used very effectively in the previous Computer Design and Computer Architecture courses, and feedback often cites the value placed on the lab exercises by students.

Outline Contents

Review of logic design and implementation technologies; from simple combinational logic to state machines for sequential circuits; logic design using Verilog and introduction to FPGAs.
Register Transfer Level design principles; registers, clocks, timing budgets, setup and hold margins, clock skew, clock-domain crossing and synchronization, metastability.
Quantitative computer architecture; performance evaluation methods and metrics, principles of high-performance design.

Processor Architecture
Instruction Set Architecture (ISA) design; instruction set classes, registers, memory addressing. RISC vs CISC, how the ISA supports high-level languages, quantitative approach to ISA design. Example ISAs (e.g. MIPS, RISC-V). ISA requirements for embedded systems.
Pipelined processor design; pipeline hazards and interlocks, control prediction techniques and their usage.
Out-of-order execution; scoreboards, reservation stations, register renaming, quantitative analysis of performance.

Computer Arithmetic and ALU Design
Introduction to binary arithmetic functions; fixed-point addition, subtraction, multiplication and division.
Advanced techniques in computer arithmetic; carry-look ahead adders, parallel-prefix adders, Booth-coded multipliers, Wallace and Dadda trees, sub-word parallelism, fractional fixed-point multiply- accumulate operations.
Floating-point computations; IEEE standard, floating-point addition and multiplication, high-performance fused-multiply-add architectures.

Memory System Design
Memory hierarchies; review of principles, quantitative analysis of memory hierarchy performance; exploring the design space of cache parameters.
Cache coherence in multi-core architectures; protocols and implementation techniques.
Main memory design; Interfacing between processor and memory, synchronous and asynchronous bus protocols.
Error detection and correction schemes; parity, Hamming codes, SECDED.

***This course replaces Computer Design (INFR09046) and Computer Architecture (INFR09009) FROM 2019/20.***
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Co-requisites
Prohibited Combinations Students MUST NOT also be taking Digital System Design 4 (ELEE10007)
Other requirements None
Information for Visiting Students
Pre-requisitesCourse Title: Informatics 2C - Introduction to Computer Systems INFR08018
High Demand Course? Yes
Course Delivery Information
Academic year 2023/24, Available to all students (SV1) Quota:  60
Course Start Semester 1
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 200 ( Lecture Hours 22, Seminar/Tutorial Hours 4, Supervised Practical/Workshop/Studio Hours 12, Feedback/Feedforward Hours 4, Summative Assessment Hours 53, Programme Level Learning and Teaching Hours 4, Directed Learning and Independent Learning Hours 101 )
Assessment (Further Info) Written Exam 60 %, Coursework 40 %, Practical Exam 0 %
Additional Information (Assessment) Assessment Weightings:
Written Examination: 60%
Practical Examination: 0%
Coursework: 40%

This course is summatively assessed using a combination of written exam and coursework exercises. The coursework reinforces lecture-based teaching by setting tasks in which students design and implement some aspect of a microprocessor, both in real hardware and also at higher levels of abstraction, using simulated systems. Therefore, a higher than normal weighting is given to the coursework (40%), with the remainder of the assessment (60%) coming from a written exam. There is no requirement to pass any individual element of the coursework.
Feedback This course uses a combination of mechanisms, including: feedforward during coursework sessions, feedback on exercise sheet solutions during scheduled feedback sessions (in the first half of the course), and feedforward/feedback through tutorial sessions (in the second half of the course). Tutorials sessions take the form of examples classes, with exam-like question sheets and guidance and feedback from tutors. Students will be provided with feedforward during the coursework sessions, involving lecturer and demonstrators discussing work with class members, with the aim of improving their skills as they develop their coursework solutions prior to hand-in.
Exam Information
Exam Diet Paper Name Hours & Minutes
Main Exam Diet S1 (December)Computer Architecture and Design (INFR10076)2:00
Resit Exam Diet (August)2:00
Learning Outcomes
On completion of this course, the student will be able to:
  1. describe the structure and operating characteristics of a high-performance microprocessor, and explain the principles of: orthogonal instruction set design; pipeline hazards and interlocks; branch prediction (both static and dynamic); out-of-order execution
  2. explain the design and operating principles of arithmetic units including: high-speed adders and multipliers; dividers; and floating-point units. And also demonstrate how selected fixed-point arithmetic functions can be implemented (in a laboratory setting)
  3. design and implement both combinational and synchronous digital systems using state-of-the-art FPGA design tools and hardware description languages
  4. describe the structure and operating characteristics of memory systems; demonstrate the ability to evaluate quantitatively the performance of a combined processor and memory system with respect to cycles-per-instruction (CPI) and memory bandwidth requirements; describe the operating principles of error detection and correction techniques applied to memory systems, and design a SECDED solution for a given memory system
  5. reason about the ways in which memory hierarchies can be configured to exploit locality in order to reduce average memory access times, and quantitatively evaluate the impact of varying cache design parameters (e.g. capacity, associativity, block size, and write policies) on performance; understand the operating principles of cache coherency protocols, and be able to compare and contrast different implementation techniques
Reading List
Textbooks - Students are strongly recommended to purchase either [1] or [5], and one from [2, 3, 4].

1. Hennessy/Patterson, Computer Architecture: A Quantitative Approach (5/e or 4/e).
2. Morris Mano, Michael D. Ciletti: Digital Design, 4/e, Prentice Hall, 2007.
3. Hamacher/Vranesic/Zaky: Computer Organization, McGraw-Hill, 2001.
4. Mano/Kime: Logic and Computer Design Fundamentals, Pearson, 2008.
5. Patterson/Hennessy: Computer Organization and Design, Elsevier, 2005.
6. Null/Lobur: The Essentials of Computer Organization and Architecture, Jones and Bartlett Publishers, 2003.
Additional Information
Graduate Attributes and Skills Students completing this course can be expected to have developed the following personal and professional attributes and skills, beyond the study of the subject itself:

The ability to exercise autonomy and initiative
Advanced skills in the field of quantitative analysis of complex digital systems
A working knowledge of how to optimize the performance of a system, using quantitative methods
A specific understanding of the industrial design processes involved in microprocessor development, and a broad understanding of the ASIC and IP businesses as delivery vehicles for digital devices
Practical skills in the design, implementation and testing of real-world digital designs, using a design flow of similar structure to that used today in industry
The ability to demonstrate originality and creativity in dealing with professional level issues
The ability to communicate effectively on a professional level with peers, senior colleagues and specialists
KeywordsComputer Design,Computer Architecture,Computer Systems,CARD
Course organiserProf Nigel Topham
Tel: (0131 6)50 5122
Course secretaryMrs Michelle Bain
Tel: (0131 6)51 7607
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