THE UNIVERSITY of EDINBURGH

DEGREE REGULATIONS & PROGRAMMES OF STUDY 2024/2025

Timetable information in the Course Catalogue may be subject to change.

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DRPS : Course Catalogue : School of Engineering : Electronics

Undergraduate Course: Digital Systems Laboratory (ELEE10023)

Course Outline
SchoolSchool of Engineering CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 10 (Year 4 Undergraduate) AvailabilityAvailable to all students
SCQF Credits10 ECTS Credits5
SummaryThe laboratory aims to produce students who are capable of developing hardware-software digital systems from high level functional specifications and prototyping them on to FPGA hardware using a standard hardware description language and software programming language.
Course description Laboratory exercise designed to teach Embedded Digital System Design, Embedded Processor Programming, Verilog Hardware Description Language, Data Path design and Control Path design through the completion of successive design tasks.
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Students MUST have passed: Digital System Design and Digital Systems Laboratory 3 (ELEE09035)
It is RECOMMENDED that students have passed Digital System Design 3 (ELEE09024)
Co-requisites It is RECOMMENDED that students also take Digital System Design 4 (ELEE10007)
Prohibited Combinations Other requirements None
Additional Costs Purchase of a Daybook
Information for Visiting Students
Pre-requisitesStudents should be familiar with digital design using Verilog, and embedded system programming.
High Demand Course? Yes
Course Delivery Information
Academic year 2024/25, Available to all students (SV1) Quota:  35
Course Start Semester 2
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 100 ( Supervised Practical/Workshop/Studio Hours 33, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 65 )
Assessment (Further Info) Written Exam 0 %, Coursework 100 %, Practical Exam 0 %
Additional Information (Assessment) Ongoing academic assessment during lab sessions through a number of checkpoints (100%).
Feedback Not entered
No Exam Information
Learning Outcomes
On completion of this course, the student will be able to:
  1. Data paths and Control paths and number of ways of designing them.
  2. Ability to use and choose between different techniques
  3. Ability to use a commercial digital system development tool suite
  4. Ability to evaluate implementation results
  5. Instruction-set based control path design
Reading List
Digital Design (Verilog): An Embedded Systems Approach using Verilog - Peter Ashenden
Additional Information
Graduate Attributes and Skills Not entered
KeywordsEmbedded Digital System Design,Embedded Processor Programming,Verilog,Data path and Control Path
Contacts
Course organiserDr Shady Agwa Rizkalla
Tel:
Email: shady.agwa@ed.ac.uk
Course secretaryMs Brunori Viola
Tel: (0131 6)50 5687
Email: vbrunori@ed.ac.uk
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