Undergraduate Course: Digital Systems Laboratory 3 (ELEE09018)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 9 (Year 3 Undergraduate) |
Availability | Available to all students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | This laboratory course builds upon second-year material, enabling students to design synchronous digital circuits from high-level functional specifications and prototype them on Field Programmable Gate Array (FPGA) hardware using standard hardware description languages (HDLs) |
| Course description |
Week 1: Hello world & Hello lots of worlds
Week 2: Hello synchronous world & shifting the world
Week 3: Shifting many worlds & counting the world
Week 4:Timing the world & decoding the world
Week 5: Timing the world in decimal & Colour the world
Week 6: Colour the world
Week 7: Assessment 1
Week 8: World of state machines & World of linked state machines
Week 9: World of linked state machines & Snake game
Week 10: Snake game
Week 11: Assessment 2
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Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
Students MUST have passed:
Digital System Design 2 (ELEE08015)
|
Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
| Additional Costs | None - If possible, boards can be lent to student to use at home in exchange for a deposit to be paid back at the end of semester |
Information for Visiting Students
| Pre-requisites | Students MUST have passed: Digital System Design 2 (ELEE08015) or equivalent |
| High Demand Course? |
Yes |
Course Delivery Information
|
| Academic year 2026/27, Available to all students (SV1)
|
Quota: None |
| Course Start |
Semester 1 |
Timetable |
Timetable |
| Learning and Teaching activities (Further Info) |
Total Hours:
100
(
Formative Assessment Hours 1,
Summative Assessment Hours 10,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
87 )
|
| Assessment (Further Info) |
Written Exam
0 %,
Coursework
100 %,
Practical Exam
0 %
|
| Additional Information (Assessment) |
100% lab-based assessment: 3 Checkpoints in total, with weight of 25%, 35% and 40%. |
| Feedback |
Not entered |
| No Exam Information |
Learning Outcomes
On completion of this course, the student will be able to:
- Demonstrate proficiency inahardware description language
- Design and implement synchronous sequential logic circuits and asynchronous combinatorial logic circuits
- Develop finite state machines using modular design principles
- Understand digital circuit development flow from functional specification through to design and simulation
- Apply synthesis, implementation, and testing processes on a practical FPGA board
|
Reading List
Digital Design, An Embedded Systems Approach Using Verilog
By Peter J Ashenden, Morgan Kaufmann, 2007, ISBN-13: 978-
0123695277 |
Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | FPGA,Verilog,Hardware Description Language |
Contacts
| Course organiser | Dr Chang Liu
Tel: (0131 6)50 2563
Email: c.liu@ed.ac.uk |
Course secretary | Ms Ilaria Monfroni
Tel:
Email: imonfron@ed.ac.uk |
|
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