Undergraduate Course: Digital System Design 4 (ELEE10007)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 10 (Year 4 Undergraduate) |
Availability | Available to all students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | This course is lecture based and is taken by students in the forth year of electronics and electrical engineering degrees in Semester 2. It comprises one 22 lecture module with 8 tutorials. It is assessed 100% by examination. The course covers: Computer Architecture ( from a hardware perspective); Components of Computers; Microprocessor Design; and Parallel Computing Architectures |
| Course description |
Typically two lectures per week with subjects covered in 2 lectures. 1-2 guest lectures on practical applications of the fundamental knowledge will be planned with topics to be determined. Main assessment by examination and feedback opportunities will include submission of example exam questions adapted from a previous version of the course.
Main Topics (subject to revision):
1. Introduction and historical perspective of computer processors
2. Modern technology and types of computers
3. Computer performance
4. Digital logic reviews
5. Instruction set architecture of RISC-V
6. Processor architecture of RISC-V
7. Pipelined processor architecture
8. Memory and Caches
9. Parallel architectures
|
Information for Visiting Students
| Pre-requisites | Students should be familiar with combinational and sequential logic circuit design, understand and be able to design state machines. They should also understand datapaths and be familiar with the associated arithmetic circuits. |
| High Demand Course? |
Yes |
Course Delivery Information
| Not being delivered |
Learning Outcomes
On completion of this course, the student will be able to:
- Differentiate different types of computers and evaluate processor performance in terms of: CPU time, instruction count, CPI, benchmarks, power consumption and cost effectiveness
- Use Instruction Set Architecture and RISC-V assembly language.
- Construct the processor architecture and datapath, mitigate hazards, and discern the differences between the single-cycle datapath and pipelined datapath.
- Organise memory and caches, including virtual memory systems
- Evaluate the performance improvements from parallel computing architectures
|
Reading List
Essential:
Computer Organization and Design RISC-V Edition
David Patterson, John Hennessy
2nd Edition, Morgan Kaufmann, 2020
ISBN: 9780128203316 |
Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | Not entered |
Contacts
| Course organiser | Dr Chang Liu
Tel: (0131 6)50 2563
Email: c.liu@ed.ac.uk |
Course secretary | Ms Ilaria Monfroni
Tel:
Email: imonfron@ed.ac.uk |
|
|
University Homepage