Undergraduate Course: Digital Electronics 3 (ELEE09009)
Course Outline
| School |
School of Engineering |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 9 (Year 3 Undergraduate) |
Credits |
20 |
| Home subject area |
Electronics |
Other subject area |
None |
| Course website |
http://www.see.ed.ac.uk/teaching/electronics/year3/digel3.html
|
Taught in Gaelic? |
No |
| Course description |
This course is lecture and laboratory based and is taken by all students taking the third year of electronics and/or electrical engineering degree in Semester 1. It comprises one 20 lecture module, Digital Circuits and the Microway embedded software coursework module.
Digital Circuits: Digital Circuits aims to build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for datapath and FSM design.
Microway: Microway aims to inculcate structured approaches to analysis, synthesis and testing, in an environment where the scale of the problem is beyond the scope of the constrained resources of any individual in the team. Hence, personal and team organisation is essential in achieving a satisfactory outcome. A general appreciation of issues in control loop stability, inter; machine communication and human-computer interaction is conveyed, through the prima facie requirements of the project. |
Information for Visiting Students
| Pre-requisites |
None |
| Displayed in Visiting Students Prospectus? |
Yes |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 1, Available to all students (SV1)
|
WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | Digital Circuits | 1-11 | | 12:10 - 13:00 | | | | | King's Buildings | Tutorial | Digital Circuits | 3-11 | 16:10 - 17:00 | | | | | | King's Buildings | Lecture | Digital Circuits | 1-11 | | | | | 12:10 - 13:00 | | King's Buildings | Tutorial | Digital Circuits | 3-11 | | | | 16:10 - 17:00 | | | King's Buildings | Laboratory | Microway | 2-11 | | | | | 11:10 - 12:00 |
| First Class |
Week 1, Tuesday, 12:10 - 13:00, Zone: King's Buildings. Lecture Theatre 6301, JCMB |
| Exam Information |
| Exam Diet |
Paper Name |
Hours:Minutes |
Stationery Requirements |
Comments |
| Main Exam Diet S1 (December) | Digital Electronics 3 | 1:30 | 12 sides | | | Resit Exam Diet (August) | | 1:30 | 12 sides | c/w u03846 |
Summary of Intended Learning Outcomes
Digital Circuits:
1.Understand the concept of synthesis and modern digital circuit design;
2.Understand the need for optimisation;
3.Understand the steps involved in synthesis and identify different types of circuits;
4.Understand design methodologies using current computer aided design tools;
5.Understand digital circuit representation formats including high level hardware description languages such as Verilog-HDL;
6.Understand the general digital circuit structure;
7.Understand the concept of static timing analysis with use of cell delay and wireload models;
8.Understand binary arithmetic, number representation and coding, including 2?s complement and floating-point representations;
9.Understand the basic datapath structures, including adders and multipliers;
10.Design and analyse small synchronous digital circuits which incorporate D, T or JK Flip Flops;
11.Implement small synchronous circuit designs using discrete gates and flip-flops and programmable logic devices;
12.Understand synchronous flip-flops, setup and hold timing constraints;
13.Understand synchronous counters, non-binary synchronous counters, generalised small synchronous design methods;
14.Understand Moore and Mealy machines, sate diagrams, ASM charts;
15.Design synchronous sequence detectors;
16.Understand Programmable Logic Devices (PLDs).
Microway:
1.Formulate algorithms, in abstract form, for the solution of problems;
2.Analyse software timing requirements and performance;
3.Analyse software arithmetic precision requirements;
4.Transform algorithms into C language implementations;
5.Use asynchronous scheduling techniques (interrupts and threads) in software design;
6.Program simple I/O device hardware, including r/o, r/w and w/o registers, using structure mapping and bit manipulation in the C language;
7.Manage software inter-process communication through queues and mailboxes.
|
Assessment Information
| 1.5 hour Examination(50%) + Laboratory work(50%) |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Not entered |
| Transferable skills |
Not entered |
| Reading list |
Fundamentals of Logic Design: fourth edition, C. H. Roth, (West Publishing Company) 1992
Application-Specific Integrated Circuits, M.J.S. Smith, (Addison Wesley) 1997, ISBN 0 201 50022 1
Digital Integrated Circuits: A Design Perspective, J.M. Rabaey, Prentice Hall (1996), ISBN 0 13 1786091
HDL Chip Design: A Practical Guide for Designing, Synthesizing, and Simulating ASICs and FPGAs using VHDL and Verilog, D.J. Smith, (Doone Publications) 1999, ISBN 0 9651934 3 8
The art of digital design, D. Winkel and F. Prosser, (Prentice hall) 1980
Electronic Logic Circuits, J.R. Gibson, (Edward Arnold) 1992
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| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords |
Not entered |
Contacts
| Course organiser |
Dr Tughrul Arslan
Tel: (0131 6)50 5592
Email: T.Arslan@ed.ac.uk |
Course secretary |
Miss Nicola Marshall
Tel: (0131 6)50 5687
Email: Nicola.Marshall@ed.ac.uk |
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copyright 2011 The University of Edinburgh -
31 January 2011 7:41 am
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