Undergraduate Course: High Level Programming of Reconfigurable Hardware 5 (ELEE11074)
Course Outline
| School |
School of Engineering |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 11 (Year 5 Undergraduate) |
Credits |
20 |
| Home subject area |
Electronics |
Other subject area |
None |
| Course website |
None
|
Taught in Gaelic? |
No |
| Course description |
The aim of this course is to produce students who are capable of designing reconfigurable hardware (FPGAs) from a high level language. |
Information for Visiting Students
| Pre-requisites |
00441 Digital Electronics or U01900 Computer Design or equivalent
AND
U00481 Electrical Engineering Methods or CS0004 Computer Programming Skills and Concepts 1 or equivalent |
| Displayed in Visiting Students Prospectus? |
Yes |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 2, Available to all students (SV1)
|
WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | | 1-11 | 10:00 - 12:00 | | | | |
| First Class |
Week 1, Monday, 09:00 - 13:00, Zone: King's Buildings. Teaching Lab A, |
| Additional information |
3 hour(s) per week for 4 week(s). |
| Exam Information |
| Exam Diet |
Paper Name |
Hours:Minutes |
Stationery Requirements |
Comments |
| Main Exam Diet S2 (April/May) | | 2:00 | 12 sides | c/w PGEE11062 |
Summary of Intended Learning Outcomes
1.Knowledge and understanding of:
I. The role of Field Programmable Gate Arrays (FPGAs) as modern computing platforms;
II. A range of FPGA design flows including High Level Language (HLL) design flows
2. Intellectual
I. Ability to choose between different FPGA design techniques, use them to develop FPGA-based applications and evaluate the resulting implementations
3. Practical
I. Ability to use an HLL-based FPGA design suite to develop applications on FPGAs
|
Assessment Information
Written Examination: 50%Practicals: 50%
Four 3-hour lab sessions would be run in this course. Students will submit the work produced at the end of each session, which will be assessed. |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Not entered |
| Transferable skills |
Not entered |
| Reading list |
Not entered |
| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords |
FPGAs, High Level Programming, Handel-C, Electronic System Level design |
Contacts
| Course organiser |
Dr Khaled Benkrid
Tel: (0131 6)50 5682
Email: K.Benkrid@ed.ac.uk |
Course secretary |
Mrs Laura Smith
Tel: (0131 6)50 5690
Email: laura.smith@ed.ac.uk |
|
copyright 2011 The University of Edinburgh -
31 January 2011 7:42 am
|
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