Postgraduate Course: Digital Systems Laboratory (MSc) (PGEE10009)
Course Outline
| School |
School of Engineering |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Not available to visiting students |
| Credit level (Normal year taken) |
SCQF Level 10 (Postgraduate) |
Credits |
10 |
| Home subject area |
Postgrad (School of Engineering) |
Other subject area |
None |
| Course website |
None
|
Taught in Gaelic? |
No |
| Course description |
The lab aims to produce students who are capable of developing hardware-software digital systems from high level functional specifications, and prototyping them on to FPGA hardware using a standard hardware description language and software programming language. |
Entry Requirements
| Pre-requisites |
|
Co-requisites |
|
| Prohibited Combinations |
|
Other requirements |
None
|
| Additional Costs |
None |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 2, Not available to visiting students (SS1)
|
WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Laboratory | | 1-11 | | 09:00 - 12:00 | | | |
| First Class |
Week 1, Tuesday, 09:00 - 12:00, Zone: King's Buildings. Teaching Lab A, Fleeming Jenkin |
| No Exam Information |
Summary of Intended Learning Outcomes
1. Knowledge and understanding of:
I. Data paths and Control paths and number of ways of designing them;
II. Instruction-set based control path design;
III. Control and data path integration;
IV. Capture the design of hardware-software digital systems in a standard hardware description language.
2. Intellectual:
I. Ability to use and choose between different techniques for digital system design and capture;
II. Ability to evaluate implementation results (e.g. speed, area, power) and correlate them with the corresponding high level design and capture.
3. Practical:
I. Ability to use a commercial digital system development tool suite to develop a hardware-software digital system and prototype them on to FPGA hardware. |
Assessment Information
| Ongoing academic assessment during lab sessions through a number of checkpoints (100%). |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Not entered |
| Transferable skills |
Not entered |
| Reading list |
Not entered |
| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords |
Embedded Digital System Design, Embedded Processor Programming, Verilog, Data path and Control Path |
Contacts
| Course organiser |
Dr Khaled Benkrid
Tel: (0131 6)50 5682
Email: K.Benkrid@ed.ac.uk |
Course secretary |
Mrs Laura Smith
Tel: (0131 6)50 5690
Email: laura.smith@ed.ac.uk |
|
copyright 2011 The University of Edinburgh -
31 January 2011 8:05 am
|
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