Undergraduate Course: Electronics 3 (ELEE09015)
Course Outline
School |
School of Engineering |
College |
College of Science and Engineering |
Course type |
Standard |
Availability |
Available to all students |
Credit level (Normal year taken) |
SCQF Level 09 (Year 3 Undergraduate) |
Credits |
20 |
Home subject area |
Electronics |
Other subject area |
None |
Course website |
http://www.see.ed.ac.uk/teaching/electronics/year3/ |
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Course description |
Digital Circuits. Aims: To build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for asynchronous sequential design.
Satway: Satway is an exercise in analogue circuit design to realise the circuitry to display a television signal as a picture on a standard oscilloscope. |
Course Delivery Information
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Delivery period: 2010/11 Full Year, Available to all students (SV1)
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WebCT enabled: Yes |
Quota: None |
Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
King's Buildings | Lecture | | 1-22 | | 12:10 - 13:50 | | | |
First Class |
First class information not currently available |
Summary of Intended Learning Outcomes
Digital Circuits:
1.Understand the concept of synthesis and modern digital circuit design;
2.Understand the need for optimisation;
3.Understand the steps involved in synthesis and identify different types of circuits;
4.Understand design methodologies using current computer aided design tools;
5.Understand digital circuit representation formats including high level hardware description languages such as Verilog-HDL;
6.Understand the general digital circuit structure;
7.Understand the concept of static timing analysis with use of cell delay and wireload models;
8.Understand binary arithmetic, number representation and coding, including 2?s complement and floating-point representations;
9.Understand the basic datapath structures, including adders and multipliers;
10.Design and analyse small synchronous digital circuits which incorporate D, T or JK Flip Flops;
11.Implement small synchronous circuit designs using discrete gates and flip-flops and programmable logic devices;
12.Understand synchronous flip-flops, setup and hold timing constraints;
13.Understand synchronous counters, non-binary synchronous counters, generalised small synchronous design methods;
14.Understand Moore and Mealy machines, sate diagrams, ASM charts;
15.Design synchronous sequence detectors;
16.Understand Programmable Logic Devices (PLDs);
17.Understand asynchronous design, flow tables and race conditions.
Satway : At the conclusion of the exercise students should:
- be able to design voltage amplifier, ramp generator and sync. pulse separator circuits.
- be able to implement a multistage amplifier design which withstands the effects of inter-stage loading between successive stages.
- be able to implement effective decoupling in a design.
- be able to integrate a number of separate stages to implement a complete working system to a written specification.
- be able to document a design that they have carried out.
- be able to layout and implement a printed circuit board design. |
Assessment Information
1.5 Hours Examination in semester 1 (50%) + Laboratory Work in semester 2 (50%) |
Please see Visiting Student Prospectus website for Visiting Student Assessment information |
Special Arrangements
Not entered |
Contacts
Course organiser |
Dr Tughrul Arslan
Tel: (0131 6)50 5592
Email: T.Arslan@ed.ac.uk |
Course secretary |
Miss Nicola Marshall
Tel:
Email: Nicola.Marshall@ed.ac.uk |
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copyright 2010 The University of Edinburgh -
1 September 2010 5:58 am
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