Undergraduate Course: Analogue Electronics (Project) 4 (ELEE10021)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Course type | Standard |
Availability | Available to all students |
| Credit level (Normal year taken) | SCQF Level 10 (Year 4 Undergraduate) |
Credits | 20 |
| Home subject area | Electronics |
Other subject area | None |
| Course website |
None |
Taught in Gaelic? | No |
| Course description | The aim of this module is to give students more hands-on experience of analogue design. It is a half-way house between discrete component design and fully custom integrated circuit design. Working with real hardware, the only way to learn about real analogue problems, will not be easy, and the practical work is likely to be very testing. However, exposure to the real problems that will be presented by using the custom chip designed specifically for this course will take the students? understanding of analogue work to a new level. |
Information for Visiting Students
| Pre-requisites | None |
| Displayed in Visiting Students Prospectus? | Yes |
Course Delivery Information
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| Delivery period: 2011/12 Full Year, Available to all students (SV1)
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WebCT enabled: Yes |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| King's Buildings | Lecture | Classroom 10, Alrick Building | 1-11 | | | | 11:10 - 12:00 | | | King's Buildings | Laboratory | | 1-11 | | | | | 10:00 - 13:00 | | King's Buildings | Lecture | Classroom 10, Alrick Building | 18-29 | 11:10 - 12:00 | | | | | | King's Buildings | Laboratory | TLD | 18-29 | | | | | 09:00 - 12:00 |
| First Class |
Week 1, Monday, 11:10 - 12:00, Zone: King's Buildings. Classroom 10, Alrick Building |
| No Exam Information |
Summary of Intended Learning Outcomes
Knowledge and understanding of the basic analogue building blocks.
Ability to perform detailed experiments and characterisation work on analogue circuits.
Ability to design and simulate operational amplifiers with a moderate performance. |
Assessment Information
| This module will be assessed by continuous assessment of practical lab work and by coursework assignments. |
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
Lectures.
Lectures exist primarily to support the practical work. Therefore, the remaining time, in which new material is introduced, is not always accurately split between lecture slots.
L1 Introduction and Overview
L2 Description of the Cadence suite $ú on-line example
L3 Description of hardware
L4 Electromigration and its effects
L5 First order MOS models, their limitations, and what can still be gained from using them. Interpretation of standard IC process rules for use in an analogue environment.
L6 Reminder of small-signal analysis as applied to MOS circuits. Important features of various standard analogue circuits that can be derived from small-signal and first-order models
L7-9 Standard components, discrete and integrated, and their limitations
L10 Revision
L11-20 Development of an on-chip band-gap reference, starting from a datasheet right through to fully simulated IC layout (including back-annotated parasitics and non-idealities).
Laboratories
The course is primarily practical: 20 labs of 3 hours assessed lab work each. Assignments are issued fortnightly
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| Transferable skills |
Not entered |
| Reading list |
CMOS Analog Integrated Circuit Design, 2nd Edition, Allen and Holberg, (The Oxford Series in Electrical and Computer Engineering) 2002, ISBN: 9780195116441.
Design of Analog CMOS Integrated Circuits, Behzad Razavi, (McGraw-Hill Science Engineering) 2000, ISBN: 9780072380323.
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| Study Abroad |
Not entered |
| Study Pattern |
Not entered |
| Keywords | Not entered |
Contacts
| Course organiser | Dr Martin Reekie
Tel: (0131 6)50 5563
Email: H.M.Reekie@ed.ac.uk |
Course secretary | Mrs Laura Smith
Tel: (0131 6)50 5690
Email: laura.smith@ed.ac.uk |
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© Copyright 2011 The University of Edinburgh - 16 January 2012 6:04 am
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