University Homepage
DRPS Homepage
DRPS Search
DRPS Contact
DRPS : Course Catalogue : School of Engineering : Electronics

Undergraduate Course: Analogue Mixed Signal Laboratory 3 (ELEE09025)

Course Outline
SchoolSchool of Engineering CollegeCollege of Science and Engineering
Credit level (Normal year taken)SCQF Level 9 (Year 3 Undergraduate) AvailabilityAvailable to all students
SCQF Credits10 ECTS Credits5
SummaryThis course is an exercise in analogue circuit design. The exercise is to design and realise the circuitry to display a television signal as a picture on a standard oscilloscope.

The exercise is designed to use knowledge gained by students in the earlier years of their course and aims to act a "structured project" to act as an introduction to the more open ended type of final year project work carried out in the fourth and fifth years. Until this point in the course the students experience is largely of analysis of circuits supplied to them. In this exercise they are expected to synthesise their own designs and realise their own circuitry.

The exercise is assessed in three stages. Firstly the students are required to produce a report in the form of a service document aimed at a service technician who is required to fault-find their design. This necessitates a circuit diagram for their design along with a PCB layout diagram and a components list. A further requirement is a brief description of the circuit and its function. Secondly the quality of the picture displayed by the final design is assessed and marked. Assessment is based on the sharpness of the picture, the contrast, sync. stability and the ramp linearity. Thirdly the physical layout and construction of the circuit is assessed for neatness and logical organisation and finally the quality of the fabrication and construction of the PCB is assessed. The criteria used for assessing the exercise are described in an appendix to the manual that is issued to each participant.
Course description Not entered
Entry Requirements (not applicable to Visiting Students)
Pre-requisites Students MUST have passed: Analogue Circuits 2 (ELEE08016) AND Electronics Project Laboratory 2A (ELEE08014) OR Electronics Project Laboratory 2B (ELEE08019) OR Electronics Project Laboratory 2C (ELEE08018)
Prohibited Combinations Other requirements None
Additional Costs None
Information for Visiting Students
Pre-requisitesFamiliarity with op-amp circuits, basic competence with electronic design, competence in the use of simple electronic test equipment.
High Demand Course? Yes
Course Delivery Information
Academic year 2015/16, Available to all students (SV1) Quota:  None
Course Start Semester 2
Course Start Date 11/01/2016
Timetable Timetable
Learning and Teaching activities (Further Info) Total Hours: 100 ( Formative Assessment Hours 1, Summative Assessment Hours 10, Programme Level Learning and Teaching Hours 2, Directed Learning and Independent Learning Hours 87 )
Assessment (Further Info) Written Exam 0 %, Coursework 100 %, Practical Exam 0 %
Additional Information (Assessment) Coursework 100%
Feedback Not entered
No Exam Information
Learning Outcomes
At the conclusion of the exercise the students should:
be able to design voltage amplifier, ramp generator and sync. pulse separator circuits.
be able to implement a multistage amplifier design which withstands the effects of inter-stage loading between successive stages.
be able to implement effective decoupling in a design.
be able to integrate a number of separate stages to implement a complete working system to a written specification.
be able to document a design that they have carried out.
be able to layout and implement a printed circuit board design.
Reading List
Additional Information
Graduate Attributes and Skills Not entered
Course organiserDr Brian Flynn
Tel: (0131 6)50 5590
Course secretaryMrs Lynn Hughieson
Tel: (0131 6)50 5687
Help & Information
Search DPTs and Courses
Degree Programmes
Browse DPTs
Humanities and Social Science
Science and Engineering
Medicine and Veterinary Medicine
Other Information
Combined Course Timetable
Important Information
© Copyright 2015 The University of Edinburgh - 18 January 2016 3:58 am