Postgraduate Course: Analogue VLSI A (ELEE11041)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 11 (Postgraduate) |
Availability | Available to all students |
| SCQF Credits | 20 |
ECTS Credits | 10 |
| Summary | The course is primarily a laboratory course that will involve two, three-hour, lab sessions plus a lecture, every week for ten weeks.
The lab is centred on a custom designed ASIC. The ASIC, which was fabricated on the AMS 0.35m CMOS process, contains a number of single transistors and small sub-circuits such as current mirrors, differential stages, a bandgap reference, a simple DAC and a set of passive components.
The ASIC is mounted on a sophisticated, purpose-designed PCB that includes a PIC, a liquid crystal display, DACs, a Direct Digital Synthesis chip and many other devices that serve to support and augment the analogue ASIC. This PCB can communicate directly with a PC via a USB link. The result is a purpose-designed mixed-signal environment where analogue and mixed signal phenomena can be examined in detail.
The whole laboratory course is supported throughout by Cadence simulation, so you will see how simulation and reality fit together, where the differences lie, and how to account for them.
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| Course description |
Lectures.
Lectures exist primarily to support the practical work. Therefore, the remaining time, in which new material is introduced, is not always accurately split between lecture slots.
L1 Introduction and Overview
L2 Description of the Cadence suite ¿ on-line example
L3 Description of hardware
L4 Electromigration and its effects
L5 First order MOS models, their limitations, and what can still be gained from using them. Interpretation of standard IC process rules for use in an analogue environment.
L6 Reminder of small-signal analysis as applied to MOS circuits. Important features of various standard analogue circuits that can be derived from small-signal and first-order models
L7-9 Standard components, discrete and integrated, and their limitations
L1 Revision
L11-2 Development of an on-chip band-gap reference, starting from a datasheet right through to fully simulated IC layout (including back-annotated parasitics and non-idealities).
Laboratories
The course is primarily practical: 2 labs of 3 hours assessed lab work each, two per week. Assignments are issued weekly.
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Entry Requirements (not applicable to Visiting Students)
| Pre-requisites |
Students MUST have passed:
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Co-requisites | |
| Prohibited Combinations | |
Other requirements | None |
Information for Visiting Students
| Pre-requisites | 2,1 Honours BEng or MEng in Electronics and Electrical Engineering, or equivalent |
| High Demand Course? |
Yes |
Course Delivery Information
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| Academic year 2015/16, Available to all students (SV1)
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Quota: None |
| Course Start |
Full Year |
Timetable |
Timetable |
| Learning and Teaching activities (Further Info) |
Total Hours:
200
(
Supervised Practical/Workshop/Studio Hours 70,
Formative Assessment Hours 1,
Summative Assessment Hours 20,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
105 )
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| Assessment (Further Info) |
Written Exam
0 %,
Coursework
100 %,
Practical Exam
0 %
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| Additional Information (Assessment) |
60% laboratory assignment, 2 class tests worth 20% each |
| Feedback |
Not entered |
| No Exam Information |
Learning Outcomes
| The students will understand fundamentals in analogue integrated circuit design. They will be able to use the most up to date industrial simulator for IC design. They will have a good amount of practical experience and will be able to relate measured results to simulated results.
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Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | analogue circuit MOS |
Contacts
| Course organiser | Dr Martin Reekie
Tel: (0131 6)50 5563
Email: H.M.Reekie@ed.ac.uk |
Course secretary | Mrs Sharon Potter
Tel: (0131 6)51 7079
Email: Sharon.Potter@ed.ac.uk |
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© Copyright 2015 The University of Edinburgh - 18 January 2016 3:59 am
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