Undergraduate Course: Digital Systems Laboratory (ELEE10023)
|School||School of Engineering
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 10 (Year 4 Undergraduate)
||Availability||Available to all students
|Summary||This lab aims to produce students who are capable of developing hardware-software digital systems from high level functional specifications, and prototyping them on to FPGA hardware using a standard hardware description language and software programming language.
Information for Visiting Students
|Pre-requisites||Students should be familiar with digital design using Verilog, and embedded system programming using C.
|High Demand Course?
Course Delivery Information
|Academic year 2017/18, Available to all students (SV1)
|Learning and Teaching activities (Further Info)
Supervised Practical/Workshop/Studio Hours 30,
Formative Assessment Hours 1,
Summative Assessment Hours 10,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
||Ongoing academic assessment during lab sessions through a number of checkpoints (100%).
|No Exam Information
On completion of this course, the student will be able to:
- Data paths and Control paths and number of ways of designing them.
- Ability to use and choose between different techniques
- Ability to use a commercial digital system development tool suite
- Ability to evaluate implementation results
- Instruction-set based control path design
|Digital Design (Verilog): An Embedded Systems Approach using Verilog - Peter Ashenden|
|Graduate Attributes and Skills
|Keywords||Embedded Digital System Design,Embedded Processor Programming,Verilog,Data path and Control Path
|Course organiser||Dr Alister Hamilton
Tel: (0131 6)50 5597
|Course secretary||Miss Megan Inch
Tel: (0131 6)51 7079