Undergraduate Course: Digital System Design 3 (ELEE09024)
|School||School of Engineering
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 9 (Year 3 Undergraduate)
||Availability||Available to all students
|Summary||This course is a lecture course and is taken by all students taking the third year of electronics and/or electrical engineering degree in Semester 1. It comprises one 22 lecture module.
Digital System Design 3 aims to build on the material presented in the second year and enhance students understanding and design skills of combinational and sequential digital circuit design techniques. To introduce the concepts and techniques for datapath and FSM design.
Logic design fundamentals. State machines, equivalent states and state reduction. Implication
Introduction to hardware description languages (HDL). Synthesis. Behavioural, structural and data
flow (register-transfer level, RTL) models.
Programmable logic devices. Simple programmable logic devices, complex programmable logic
devices, field programmable gate arrays, programmable SoCs.
Design Examples. Data path, controller model.
Adders. Critical path, carry-lookahead adder, parallel prefix adder.
Multipliers. Add and shift multiplier, array multiplier. Signed integer/fraction multiplier.
State machine charts. Microprogramming.
Designing with FPGAs. Shannon¿s decomposition. Carry chains. Cascade chains. Dedicated
multipliers. Dedicated memory. Cost of programmability. Design translation (Synthesis). Mapping,
placement and routing.
Floating point arithmetic. Multiplication and addition.
Verification of digital systems. Functional verification. Timing verification.
Information for Visiting Students
|Pre-requisites||Must have understanding and knowledge of: Boolean Algebra, logic gates, Combinational logic design, minimisation of combinational logic (e.g. Karnaugh Maps), basic sequential circuit design.
|High Demand Course?
Course Delivery Information
|Academic year 2018/19, Available to all students (SV1)
|Course Start Date
|Learning and Teaching activities (Further Info)
Lecture Hours 22,
Seminar/Tutorial Hours 22,
Formative Assessment Hours 1,
Summative Assessment Hours 2,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
||100% written examination.
||Hours & Minutes
|Main Exam Diet S1 (December)||1:30|
|Resit Exam Diet (August)||1:30|
On completion of this course, the student will be able to:
- Understand the concept of synthesis and modern digital circuit design using hardware description languages (HDL)
- Understand basic datapath structures, including adder and multiplier architectures
- Under the design of combinational and sequential logic systems including finite state machines and state reduction
|Digital Systems Design Using VHDL, 3rd (international) edition, Charles H. Roth, Jr. and Lizy Kurian John. Publisher: Cengage Learning ISBN-13: 978-1-305-63892-1|
Digital Design (Verilog): An Embedded Systems Approach Using Verilog (26 Oct 2007)by Peter Ashenden (Author)
FSM based Digital Design using Verilog HDL by Peter Minns and Ian Elliot
Pub: Wiley (208)
|Graduate Attributes and Skills
|Keywords||digital circuits,combinational logic,sequential logic,FSM,finite state machine,datapath,adder
|Course organiser||Dr Alister Hamilton
Tel: (0131 6)50 5597
|Course secretary||Mrs Laura Robinson
Tel: (0131 6)50 5053