Undergraduate Course: Digital System Design and Digital Systems Laboratory 3 (ELEE09035)
|School||School of Engineering
||College||College of Science and Engineering
|Credit level (Normal year taken)||SCQF Level 9 (Year 3 Undergraduate)
||Availability||Available to all students
|Summary||This course aims to build on the material presented in second year and to give the students an intuitive feel for the basic building blocks of digital systems.
The lecture course seeks to enhance student understanding of digital system design. The course provides an introduction to hardware description languages, a broad overview of programmable logic devices and further illustration of data path / controller model design examples. There is a focus on adder and multiplier architectures and computer arithmetic. A Reduced Instruction Set Computing (RISC) microprocessor architecture is outlined. Verification of digital systems is introduced.
The purpose of this laboratory course is to produce students who are capable of developing synchronous digital circuits from high level functional specifications and prototyping them on FPGA hardware using a standard hardware description language (HDL).
Logic design fundamentals. State machines, equivalent states and state reduction. Implication charts.
Introduction to hardware description languages (HDL). Synthesis. Behavioural, structural and data flow (register-transfer level, RTL) models.
Programmable logic devices. Simple programmable logic devices, complex programmable logic devices, field programmable gate arrays, programmable SoCs.
Design examples using data path, controller model.
Adders. Critical path, carry-lookahead adder, parallel prefix adder.
Multipliers. Add and shift multiplier, array multiplier. Signed integer/fraction multiplier.
State machine charts. Microprogramming.
Design translation (Synthesis). Mapping, placement and routing.
Floating point arithmetic. Multiplication and addition.
Introduction to design of RISC microprocessors.
Introduction to verification of digital systems. Functional verification. Timing verification.
Week 1: Hello world & Hello lots of worlds
Week 2: Hello synchronous world & shifting the world
Week 3: Shifting many worlds & counting the world
Week 4: Timing the world & decoding the world
Week 5: Timing the world in decimal & Colour the world
Week 6: Colour the world
Week 7: Assessment 1
Week 8: World of state machines & World of linked state machines
Week 9: World of linked state machines & Snake game
Week 10: Snake game
Week 11: Assessment 2
Information for Visiting Students
|Pre-requisites||Knowledge of basic digital circuit theory.
|High Demand Course?
Course Delivery Information
|Academic year 2022/23, Available to all students (SV1)
|Learning and Teaching activities (Further Info)
Lecture Hours 22,
Seminar/Tutorial Hours 11,
Supervised Practical/Workshop/Studio Hours 30,
Summative Assessment Hours 3,
Programme Level Learning and Teaching Hours 4,
Directed Learning and Independent Learning Hours
|Assessment (Further Info)
|Additional Information (Assessment)
||Written exam: 50%
||Hours & Minutes
|Main Exam Diet S1 (December)||1:30|
|Resit Exam Diet (August)||1:30|
On completion of this course, the student will be able to:
- Understand data path structures, including adder and multiplier architectures and computer arithmetic;
- Understand the design of finite state machines, the use of state reduction techniques and simple RISC microprocessor architectures;
- Master a hardware description language, Verilog. Implement synchronous sequential logic, asynchronous combinatorial logic and state machine in a modular manner;
- Understand digital circuit development flow from capturing functional specification, design, simulation, to synthesis and implementation, until testing on a practical FPGA board.
|Digital Systems Design Using VHDL, 3rd (international) edition, Charles H. Roth, Jr. and Lizy Kurian John. Publisher: Cengage Learning ISBN-13: 978-1-305-63892-1|
Digital Design, An Embedded Systems Approach Using Verilog, Peter J Ashenden, Morgan Kaufmann, 2007, ISBN-13: 978-0123695277
FSM based Digital Design using Verilog HDL by Peter Minns and Ian Elliot. Pub: Wiley (2008) ISBN:978-0470-06070-4
|Graduate Attributes and Skills
|Keywords||Digital circuits,digital system,adder,multiplier,state machine,FSM,Verilog,FPGA
|Course organiser||Dr Alister Hamilton
Tel: (0131 6)50 5597
|Course secretary||Ms Brunori Viola
Tel: (0131 6)50 5687