Undergraduate Course: Digital Systems Laboratory (ELEE10023)
Course Outline
| School | School of Engineering |
College | College of Science and Engineering |
| Credit level (Normal year taken) | SCQF Level 10 (Year 4 Undergraduate) |
Availability | Available to all students |
| SCQF Credits | 10 |
ECTS Credits | 5 |
| Summary | The laboratory aims to produce students who are capable of developing hardware-software digital systems from high level functional specifications and prototyping them on to FPGA hardware using a standard hardware description language and software programming language. |
| Course description |
Laboratory exercise designed to teach Embedded Digital System Design, Embedded Processor Programming, Verilog Hardware Description Language, Data Path design and Control Path design through the completion of successive design tasks.
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Information for Visiting Students
| Pre-requisites | Students should be familiar with digital design using Verilog, and embedded system programming. |
| High Demand Course? |
Yes |
Course Delivery Information
|
| Academic year 2025/26, Available to all students (SV1)
|
Quota: 36 |
| Course Start |
Semester 2 |
Timetable |
Timetable |
| Learning and Teaching activities (Further Info) |
Total Hours:
100
(
Supervised Practical/Workshop/Studio Hours 33,
Programme Level Learning and Teaching Hours 2,
Directed Learning and Independent Learning Hours
65 )
|
| Assessment (Further Info) |
Written Exam
0 %,
Coursework
100 %,
Practical Exam
0 %
|
| Additional Information (Assessment) |
Ongoing academic assessment during lab sessions through a number of checkpoints (100%). |
| Feedback |
Not entered |
| No Exam Information |
Learning Outcomes
On completion of this course, the student will be able to:
- Data paths and Control paths and number of ways of designing them.
- Ability to use and choose between different techniques
- Ability to use a commercial digital system development tool suite
- Ability to evaluate implementation results
- Instruction-set based control path design
|
Reading List
| Digital Design (Verilog): An Embedded Systems Approach using Verilog - Peter Ashenden |
Additional Information
| Graduate Attributes and Skills |
Not entered |
| Keywords | Embedded Digital System Design,Embedded Processor Programming,Verilog,Data path and Control Path |
Contacts
| Course organiser | Dr Alexantrou Serb
Tel:
Email: aserb@exseed.ed.ac.uk |
Course secretary | Ms Viola Brunori
Tel: (0131 6)50 5687
Email: vbrunori@ed.ac.uk |
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