Undergraduate Course: Informatics 2C - Introduction to Computer Systems (INFR08018)
Course Outline
| School |
School of Informatics |
College |
College of Science and Engineering |
| Course type |
Standard |
Availability |
Available to all students |
| Credit level (Normal year taken) |
SCQF Level 8 (Year 2 Undergraduate) |
Credits |
10 |
| Home subject area |
Informatics |
Other subject area |
None |
| Course website |
http://www.inf.ed.ac.uk/teaching/courses/inf2c-cs/
|
Taught in Gaelic? |
No |
| Course description |
This course is concerned with the design, implementation and engineering of digital computer systems. It offers an introduction to the internal structure of digital computers.
|
Information for Visiting Students
| Pre-requisites |
none |
| Displayed in Visiting Students Prospectus? |
No |
Course Delivery Information
|
| Delivery period: 2010/11 Semester 1, Available to all students (SV1)
|
WebCT enabled: No |
Quota: None |
| Location |
Activity |
Description |
Weeks |
Monday |
Tuesday |
Wednesday |
Thursday |
Friday |
| Central | Lecture | | 1-11 | | 15:00 - 15:50 | | | | | Central | Lecture | | 1-11 | | | | | 15:00 - 15:50 |
| First Class |
Week 1, Tuesday, 15:00 - 15:50, Zone: Central. Lecture Theatre C, David Hume Tower |
| Exam Information |
| Exam Diet |
Paper Name |
Hours:Minutes |
Stationery Requirements |
Comments |
| Main Exam Diet S1 (December) | | 1:00 | 8 sides / pencils / rubbers | | | Resit Exam Diet (August) | | 1:00 | 8 sides / pencils / rubbers | |
Summary of Intended Learning Outcomes
- Demonstrate an understanding of binary representation and basic operations on binary data.
- Demonstrate an understanding of key concepts in computer architecture, including: exceptions, interrupts, virtual memory, processes and pipelined execution.
- Sketch the design of a simple processor and explain how it operates.
- Demonstrate knowledge of I/O devices and the means by which they interface to a processor and its memory system.
- Demonstrate an understanding of the design and operation of important combinational and sequential components within a processor, such as adders, registers, and state machines.
- Demonstrate understanding of an execution pipeline, based on the MIPS architecture.
|
Assessment Information
Written Examination - 75%
Assessed Assignments - 25%
Oral Presentations - 0%
There will be at least one assessed exercise.
|
Special Arrangements
| None |
Additional Information
| Academic description |
Not entered |
| Syllabus |
The primary aim of the course is to convey an understanding of the internal structure and implementation of digital computers. To impart this knowledge, we first explain how the interface between hardware and software is typically constructed. This interface consists of several key components:
* The binary representation and manipulation of atomic data.
* The structure of a typical instruction set.
* The environment in which a program executes, and the notion of processes and virtual memory.
In addition to explaining the interface between hardware and software, this course introduces the ideas behind the hardware implementation of a processor. This consists of several further components:
* Combinational logic - how simple stateless building blocks such as adders, multiplexers and decoders can be constructed from logic
elements.
* Sequential logic - how components with state, such as latches,
registers, register files and memories can be constructed from logic elements.
* Processor structure - how a simple instruction set can be implemented using combinational and sequential logic components.
This material is prefaced by a brief introduction to the C programming language, which is widely used as a systems programming language.
|
| Transferable skills |
Not entered |
| Reading list |
* D.A. Patterson and J.L. Hennessy, Computer Organisation and Design 2/e, Morgan Kaufmann, 1998
* A. Silbershatz and P.B. Galvin, Operating Systems Concepts, 5/e, Wiley, 1998
* B.W. Kernighan and D.M. Ritchie, The C Programming Language, 2/e, Prentice Hall PTR, 1998
|
| Study Abroad |
Not entered |
| Study Pattern |
Lectures 15
Tutorials 5
Timetabled Laboratories 4
Non-timetabled assessed assignments 25
Private Study/Other 51
Total 100
|
| Keywords |
Not entered |
Contacts
| Course organiser |
Dr Jacques Fleuriot
Tel: (0131 6)50 9342
Email: Jacques.Fleuriot@ed.ac.uk |
Course secretary |
Ms Kendal Reid
Tel: (0131 6)50 5194
Email: kr@inf.ed.ac.uk |
|
copyright 2011 The University of Edinburgh -
31 January 2011 7:51 am
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